US4338616A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain
Assignee: Xerox Corp
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Filing: 1980-02-19
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Granted: 1982-07-06
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Expires: 2000-02-19
Abstract
Abstract A semi-conductor structure and particularly a high speed VLSI Self-Aligned Schottky Metal Semi-Conductor Field Effect Transistor with buried source and drain, fabricated by the ion implantation of source and drain areas at a predetermined range of depths followed by very localized laser annealing to electrically reactivate the amorphous buried source and drain areas thereby providing effective vertical separation of the channel from the buried source and drain respectively. Accordingly, spatial separations between the self-aligned gate-to-drain, and gate-to-source can be relatively very closely controlled by varying the doping intensity and duration of the implantation thereby reducing the series resistance and increasing the operating speed.
Inventors
- 👤 Izya Bol
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10D62/80; H10D62/83; H10P; H10P34/00; H10P34/40; H10P34/42
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
198 words
A high speed Schottky barrier field effect transistor with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a drain region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; and means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved.
Claim 2
Dependent Claim
198 words
A high speed Schottky barrier field effect transistor with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a drain region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; and means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved.
Claim 3
Dependent Claim
243 words
A high speed Schottky barrier field effect transistor, with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a draining region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved; and the distance between the top surfaces of said source and drain regions to the bottom surface of said channel layer each being very small whereby the transistor has low values of source-gate and gate-drain series resistance and, accordingly, said transistor can operate at high frequency.
Claim 4
Dependent Claim
243 words
A high speed Schottky barrier field effect transistor, with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a draining region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved; and the distance between the top surfaces of said source and drain regions to the bottom surface of said channel layer each being very small whereby the transistor has low values of source-gate and gate-drain series resistance and, accordingly, said transistor can operate at high frequency.
Claim 5
Dependent Claim
246 words
A high speed Schottky barrier field effect transistor, with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a drain region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved; and the distance between the top surfaces of said source and drain regions to the bottom surface of said channel layer each being no greater than 2500 Angstroms whereby the transistor has low values of source-gate and gate-drain series resistance and, accordingly, said transistor can operate at high frequency.
Claim 6
Dependent Claim
246 words
A high speed Schottky barrier field effect transistor, with low series resistance, comprising: a substrate of one conductivity type; a channel layer of the other conductivity type extended downward from a major surface of said substrate; a source region of said other conductivity type buried within said substrate below said channel layer; a drain region of said other conductivity type buried within said substrate below said channel layer; Schottky barrier gate means forming a rectifying junction with a portion of said channel, said gate means providing, when properly biased, control of the current flow between said source region and said drain region; said barrier gate means being disposed between said source and drain regions in the horizontal direction, with one edge of said barrier gate means being aligned substantially vertically with an edge of said source region and with another edge of said barrier gate means being aligned substantially vertically with an edge of said drain region; means for providing electrical contact to said source region, said drain region and said gate means, whereby a current flow path from said source region through a portion of said channel and to said drain region can be controllably achieved; and the distance between the top surfaces of said source and drain regions to the bottom surface of said channel layer each being no greater than 2500 Angstroms whereby the transistor has low values of source-gate and gate-drain series resistance and, accordingly, said transistor can operate at high frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |