Semiconductor device with operating voltage coupling region

Claim 2

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having first and second opposite surfaces; a semiconductor layer of a second conductivity type opposite to said first conductivity type, said semiconductor layer formed on said first surface of said substrate; a plurality of semiconductor regions spaced apart from one another in a surface of said semiconductor layer to form an active device, said plurality of semiconductor regions including a first semiconductor region of said first conductivity type to which an operating voltage must be coupled to power said active device; a power source voltage terminal coupled to said second surface of said substrate for receiving said operating voltage; and coupling means for coupling said operating voltage from said power source voltage terminal to said first semiconductor region, said coupling means comprising a second semiconductor region of said first conductivity type, said second semiconductor region being formed below and in contact with said first semiconductor region, said second semiconductor region having an impurity concentration level lower than the impurity concentration level of said first semiconductor region and said second semiconductor region being formed sufficiently deep into said semiconductor layer wherein said operating voltage applied to said terminal is supplied to said first semiconductor region through said substrate, said semiconductor layer, and said second semiconductor region to power said active device.

Claim 3

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having first and second opposite surfaces; a semiconductor layer of a second conductivity type opposite to said first conductivity type, said semiconductor layer formed on said first surface of said semiconductor substrate; a plurality of semiconductor regions spaced apart from one another in a surface of said semiconductor layer to form an active device, said plurality of semiconductor regions including a first semiconductor region of said first conductivity type to which an operating voltage must be applied to power said active device; a power source voltage terminal connected to said second surface of said substrate for receiving said operating voltage; coupling means for coupling said operating voltage from said power source voltage terminal to said first semiconductor region, said coupling means comprising a second semiconductor region of said first conductivity type, said second semiconductor region being formed below and in contact with said first semiconductor region, said second semiconductor region having an impurity concentration level lower than the impurity concentration level of said first semiconductor region, and said second semiconductor region being formed sufficiently deep into said semiconductor layer wherein said operating voltage applied to said terminal is supplied to said first semiconductor region through said substrate, said semiconductor layer, and said second semiconductor region to power said active device; a third semiconductor region of said first conductivity type and a substantially the same impurity concentration as said first semiconductor region, said third semiconductor region being formed in the surface of said semiconductor layer and spaced apart from said first semiconductor region; and a gate region formed between said first and third semiconductor regions, wherein said first semiconductor region, said third semiconductor region, and said gate region constitute a MOS type transistor.

Claim 4

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having first and second opposite surfaces; a semiconductor layer of a second conductivity type opposite to said first conductivity type, said semiconductor layer formed on said first surface of said semiconductor substrate; a plurality of semiconductor regions spaced apart from one another in a surface of said semiconductor layer to form an active device, said plurality of semiconductor regions including a first semiconductor region of said first conductivity type to which an operating voltage must be applied to power said active device; a power source voltage terminal connected to said second surface of said substrate for receiving said operating voltage; coupling means for coupling said operating voltage from said power source voltage terminal to said first semiconductor region, said coupling means comprising a second semiconductor region of said first conductivity type, said second semiconductor region being formed below and in contact with said first semiconductor region, said second semiconductor region having an impurity concentration level lower than the impurity concentration level of said first semiconductor region, and said second semiconductor region being formed sufficiently deep into said semiconductor layer wherein said operating voltage applied to said terminal is supplied to said first semiconductor region through said substrate, said semiconductor layer, and said second semiconductor region to power said active device; a third semiconductor region of said first conductivity type and a substantially the same impurity concentration as said first semiconductor region, said third semiconductor region being formed in the surface of said semiconductor layer and spaced apart from said first semiconductor region; and a gate region formed between said first and third semiconductor regions, wherein said first semiconductor region, said third semiconductor region, and said gate region constitute a MOS type transistor.

Claim 5

A device according to claim 1 wherein said second semiconductor region is spaced apart from said semiconductor substrate.

Claim 6

A device according to claim 3 wherein one of said plurality of said semiconductor regions includes a third semiconductor region which is of the same impurity concentration as that of said first semiconductor region and which is formed in the surface of said semiconductor layer and spaced apart from said first semiconductor region.

Claim 7

A device according to claim 4 wherein said active device includes a first transistor which has said first semiconductor region as a drain region and said third semiconductor region as a source region.

Claim 8

A device according to claim 5 wherein said first transistor includes a MOS type field-effect transistor including a conductive layer formed insulatively on a surface of said semiconductor layer between said first and third semiconductor regions.

Claim 9

A device according to claim 6 wherein said MOS transistor is a depletion type.

Claim 10

A device according to claim 6 wherein said MOS transistor is an enhancement type.

Claim 11

A device according to claim 2, 7 or 8 wherein said active device further includes a second transistor which comprises a fourth semiconductor region of substantially the same impurity concentration and same impurity type as that of said first semiconductor region, said fourth semiconductor region formed in the surface of said semiconductor layer, said second transistor having said third semiconductor region as a drain and said fourth semiconductor region as a source.

Claim 12

A device according to claim 9 wherein said second transistor includes a MOS type field-effect transistor including a conductive layer formed insulatively on a surface of said semiconductor layer between said third and fourth semiconductor regions.

Claim 13

A device according to claim 4 wherein said active device comprises a resistor layer connected between said first and third semiconductor regions and formed insulatively on the surface of said semiconductor layer therebeween, and a fourth semiconductor region of substantially the same impurity concentration and same impurity type as that of said first semiconductor region; and wherein a transistor is formed having said third semiconductor region as a drain region and said fourth semiconductor region as a source region.

Claim 14

A device according to claim 11 wherein said transistor constitutes a MOS type field-effect transistor including a conductive layer formed insulatively on a surface area of said semiconductor layer between said third and fourth semiconductor regions.

Claim 15

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having first and second opposite surfaces; a semiconductor layer of a second conductivity type opposite to said first conductivity type formed on said first surface of said semiconductor substrate; a first semiconductor region of said first conductivity type formed in a surface of said semiconductor layer; at least two semiconductor regions of said second conductivity type formed spaced apart from one another in a surface of said first semiconductor region to form an active device, one of said at least two semiconductor regions being a second semiconductor region of said second conductivity type to which an operating voltage must be applied to power said active device; a power source voltage terminal connected to said second surface of said substrate for receiving said operating voltage, said first semiconductor region being formed with an impurity concentration level lower than the impurity concentration level of said second semiconductor region and said first semiconductor region being formed sufficiently deep into said semiconductor layer wherein said operating voltage applied to said terminal is supplied to said second semiconductor region through said substrate, said semiconductor layer, and said first semiconductor region to power said active device.

Claim 16

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having first and second opposite surfaces; a semiconductor layer of a second conductivity type opposite to said first conductivity type formed on said first surface of said semiconductor substrate; a first semiconductor region of said first conductivity type formed in a surface of said semiconductor layer; at least two semiconductor regions of said second conductivity type formed spaced apart from one another in a surface of said first semiconductor region to form an active device, one of said at least two semiconductor regions being a second semiconductor region of said second conductivity type to which an operating voltage must be applied to power said active device; a power source voltage terminal connected to said second surface of said substrate for receiving said operating voltage, said first semiconductor region being formed with an impurity concentration level lower than the impurity concentration level of said second semiconductor region and said first semiconductor region being formed sufficiently deep into said semiconductor layer wherein said operating voltage applied to said terminal is supplied to said second semiconductor region through said substrate, said semiconductor layer, and said first semiconductor region to power said active device.

Claim 17

A device according to claim 13 wherein one of said at least two semiconductor regions is a third semiconductor region of said second conductivity type and of substantially the same impurity concentration as that of said second semiconductor region, which third semiconductor region is formed in the surface of said first semiconductor region and spaced apart from said second semiconductor region, wherein a transistor is formed having said second semiconductor region as a source region and said third semiconductor region as a drain region.

Claim 18

A device accoring to claim 14 wherein fourth and fifth semiconductor regions of said first conductivity type are formed in the surface of said semiconductor layer spaced apart from each other and from said first semiconductor region.

Claim 19

A device according to claim 15 wherein a transistor is formed having said fourth semiconductor region as a drain region and said fifth semiconductor region as a source region.

Claim 20

A device according to claim 16 further including a conductive layer formed insulatively on a surface of said semiconductor layer between said second and third semiconductor regions.

Claim 21

A device according to claim 17 wherein a conductive layer is formed insulatively on a surface of said semiconductor layer between said fourth and fifth semiconductor regions.

Claim 22

A device according to claim 18 further including a well region surrounding said fourth and fifth semiconductor regions.