US4472643A
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Dynamic signal generation circuit
Assignee: Toshiba Corp
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Filing: 1981-09-22
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Granted: 1984-09-18
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Expires: 2001-09-22
Abstract
Abstract A dynamic signal generation circuit comprising a semiconductor circuit for receiving two input clock signals φ and φ out of phase with each other and providing a first output signal φ1, said first output signal φ1 rising in synchronism to the leading edge of said input clock signal φ, assuming a floating state after the lapse of a predetermined period of time falling in synchronism to the trailing edge of said input clock signal φ, and a second output signal φ2, said second output signal φ2 falling in synchronism to the occurrence of the floating state of said input signal φ1 and rising in synchronism to the trailing edge of said input clock signal φ, a transistor circuit including a first and a second enhancement type transistor cascade connected between a V DD and a V SS power supply terminal, said first output signal φ1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistor, said second output signal φ2 from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor, a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors, and a depletion type transistor connected between said V DD power supply terminal and said V SS power supply terminal, the gate of the depletion type transistor being connected to a point at a potential substantially same as the potential on said node between said first and second transistors.
Inventors
- 👤 Toru Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:52
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
323 words
A dynamic signal generation circuit comprising: a semiconductor circuit for receiving two input clock signals φ and φ out of phase with each other and providing a first output signal φ1, said first output signal φ1 rising in synchronism to the leading edge of said input clock signal φ, assuming a floating state after the lapse of a predetermined period of time and falling in synchronism to the trailing edge of said input clock signal φ, and a second output signal φ2, said second output signal φ2 falling in synchronism to the occurrence of the floating state of said input signal φ1 and rising in synchronism to the trailing edge of said input clock signal φ; first and second power supply terminals; a first transistor circuit including first and second enhancement type transistors cascode connected between said first and second power supply terminals, said first output signal φ1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistors, said second output signal φ2 from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor; a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors; a second transistor circuit including third and fourth enhancement type transistors cascode connected between said first and said second power supply terminals, said first output signal φ1 being impressed upon the gate of said third enhancement type transistor, said second output signal φ2 being impressed upon the gate of said fourth enhancement type transistor; and a first depletion type transistor connected in the current path of said second transistor circuit, the conduction channel of the first depletion type transistor extending along said current path of said second transistor circuit, and the gate of the first depletion type transistor being connected to a potential substantially the same as the potential on said node between said first and second enhancement type transistors.
Claim 2
Dependent Claim
323 words
A dynamic signal generation circuit comprising: a semiconductor circuit for receiving two input clock signals φ and φ out of phase with each other and providing a first output signal φ1, said first output signal φ1 rising in synchronism to the leading edge of said input clock signal φ, assuming a floating state after the lapse of a predetermined period of time and falling in synchronism to the trailing edge of said input clock signal φ, and a second output signal φ2, said second output signal φ2 falling in synchronism to the occurrence of the floating state of said input signal φ1 and rising in synchronism to the trailing edge of said input clock signal φ; first and second power supply terminals; a first transistor circuit including first and second enhancement type transistors cascode connected between said first and second power supply terminals, said first output signal φ1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistors, said second output signal φ2 from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor; a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors; a second transistor circuit including third and fourth enhancement type transistors cascode connected between said first and said second power supply terminals, said first output signal φ1 being impressed upon the gate of said third enhancement type transistor, said second output signal φ2 being impressed upon the gate of said fourth enhancement type transistor; and a first depletion type transistor connected in the current path of said second transistor circuit, the conduction channel of the first depletion type transistor extending along said current path of said second transistor circuit, and the gate of the first depletion type transistor being connected to a potential substantially the same as the potential on said node between said first and second enhancement type transistors.
Claim 3
Dependent Claim
31 words
The dynamic signal generation circuit according to claim 1, wherein the gate of said first depletion type transistor is connected to the node between said third and fourth enhancement type transistors.
Claim 4
Dependent Claim
31 words
The dynamic signal generation circuit according to claim 1, wherein the gate of said first depletion type transistor is connected to the node between said first and second enhancement type transistors.
Claim 5
Dependent Claim
71 words
The dynamic signal generation circuit according to claim 1, which further comprises a second depletion type transistor connected in the current path of said first transistor circuit, the conduction channel of the second depletion type transistor extending along said current path of said first transistor circuit, and having its gate connected to a potential substantially the same as the potential at said node between said first and second enhancement type transistors.
Claim 6
Dependent Claim
54 words
The dynamic signal generation circuit according to claim 4, wherein the gate of said first depletion type transistor is connected to the node between said third and fourth enhancement type transistors, and also the gate of said second depletion type transistor is connected to the node between said first and second enhancement type transistors.
Claim 7
Dependent Claim
33 words
The dynamic signal generation circuit according claim 4, wherein the gates of said first and second depletion type transistors are both connected to the node between said first and second enhancement type transistors.
Claim 8
Dependent Claim
34 words
The dynamic signal generation circuit according to claim 4, wherein the gates of said first and second depletion type transistors are both connected to the node between said third and fourth enhancement type transistors.
Claim 9
Dependent Claim
269 words
A dynamic signal generation circuit comprising: a semiconductor circuit for receiving two input clock signals φ and φ out of phase with each other and providing a first output signal φ1, said first output signal φ1 rising in synchronism to the leading edge of said input clock signal φ, assuming a floating state after the lapse of a predetermined period of time and falling in synchronism to the trailing edge of said input clock signal φ, and a second output signal φ2, said second output signal φ2 falling in synchronism to the occurrence of the floating state of said input signal φ1 and rising in synchronism to the trailing edge of said input clock signal φ; first and second power supply terminals; a first transistor circuit including first and second enhancement type transistors cascode connected between said first and second power supply terminals, said first output signal φ1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistor, said second output signal φ2, from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor; a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors; and a first depletion type transistor connected in the current path of said first transistor circuit, the conduction channel of the first depletion type transistor extending along said current path of said first transistor circuit, and the gate of the first depletion type transistor being connected to a potential substantially the same as the potential on said node between said first and second enhancement type transistors.
Claim 10
Dependent Claim
269 words
A dynamic signal generation circuit comprising: a semiconductor circuit for receiving two input clock signals φ and φ out of phase with each other and providing a first output signal φ1, said first output signal φ1 rising in synchronism to the leading edge of said input clock signal φ, assuming a floating state after the lapse of a predetermined period of time and falling in synchronism to the trailing edge of said input clock signal φ, and a second output signal φ2, said second output signal φ2 falling in synchronism to the occurrence of the floating state of said input signal φ1 and rising in synchronism to the trailing edge of said input clock signal φ; first and second power supply terminals; a first transistor circuit including first and second enhancement type transistors cascode connected between said first and second power supply terminals, said first output signal φ1 from said semiconductor circuit being impressed upon the gate of said first enhancement type transistor, said second output signal φ2, from said semiconductor circuit being impressed upon the gate of said second enhancement type transistor; a capacitor circuit connected between the gate of said first transistor and the node between said first and second transistors; and a first depletion type transistor connected in the current path of said first transistor circuit, the conduction channel of the first depletion type transistor extending along said current path of said first transistor circuit, and the gate of the first depletion type transistor being connected to a potential substantially the same as the potential on said node between said first and second enhancement type transistors.
Claim 11
Dependent Claim
32 words
The dynamic signal generation circuit according to claim 8, wherein said first and second enhancement type transistors are cascode connected between said first depletion type transistor and said second power supply terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |