US4190897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary coded decimal addressed Read-Only-Memory
Assignee: Texas Instruments Inc
•
Filing: 1977-04-01
•
Granted: 1980-02-26
•
Expires: 1997-04-01
Abstract
Abstract A Read-Only-Memory (ROM) is addressed with a binary coded decimal (BCD) address in an address register or program counter. The ROM comprises an array of memory cells with associated row and column lines for addressing the array. Row and column decoders responsive to the address in the address register identify a unique row and column line for each BCD address. The row and column decoders comprise a plurality of decoders in cascaded levels. The decorders in any given level decode particular bits of the address in the address register; these decoders decode a one-out-of-a-prime-number, which prime number is a factor of the number of memory locations in the array.
Inventors
- 👤 Ashok H. Someshwar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:12
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/001; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
A binary coded decimal read-only-memory system comprising: (a) an array having rows and columns of memory cells, (b) row lines and column lines associated with said array, (c) an address register, (d) a one bit adder and binary coded decimal corrector for incrementing the address in said address register in response to a control signal and for automatically maintaining said address in binary coded decimal format, and (e) menas for addressing said array via said row and column lines with the address in said address register, said addressing means being responsive to the binary coded decimal address in said address register for addressing selected row and column lines in said array and being non-responsive to non-binary coded decimal addresses for addressing any selected row and column lines thereby, said addressing means comprising a plurality of decoders, said decoders being cascaded in a plurality of levels, the decoders in any given level being responsive to a preselected portion of the binary coded decimal address in said address register.
Claim 2
Dependent Claim
167 words
A binary coded decimal read-only-memory system comprising: (a) an array having rows and columns of memory cells, (b) row lines and column lines associated with said array, (c) an address register, (d) a one bit adder and binary coded decimal corrector for incrementing the address in said address register in response to a control signal and for automatically maintaining said address in binary coded decimal format, and (e) menas for addressing said array via said row and column lines with the address in said address register, said addressing means being responsive to the binary coded decimal address in said address register for addressing selected row and column lines in said array and being non-responsive to non-binary coded decimal addresses for addressing any selected row and column lines thereby, said addressing means comprising a plurality of decoders, said decoders being cascaded in a plurality of levels, the decoders in any given level being responsive to a preselected portion of the binary coded decimal address in said address register.
Claim 3
Dependent Claim
39 words
The binary coded decimal read-only-memory system according to claim 1, wherein said preselected portion has a maximum binary address which is equivalent to the decimal equivalent of the largest number used in each digit position in said address register.
Claim 4
Dependent Claim
105 words
The system according to claim 1, wherein said address register stores a plurality of binary coded decimal digits, wherein the largest number stored in the nonmost significant digit positions is the number nine and wherein the largest number stored in the most significant digit position in a preselected number and wherein said plurality of levels of cascaded decoders includes a level of one-of-two decoders and a level of one-of-five decoders for each non-most significant digit position in said address register, each of said levels of decoders comprising one or more decoders and being coupled to either the row or column lines associated with said array.
Claim 5
Dependent Claim
43 words
The system according to claim 3, further including at least one level of decoders for decoding the bits in the most significant digit position in said address register, said level being coupled to either the row or column lines associated with said array.
References Cited (Backward Citations)
US3921142A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-25 | 1983-08-27 | 1984-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-25 | 1987-08-27 | 1988-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-25 | 1991-08-27 | 1992-02-26 | $7700.00 | Window Closed / Lapsed |