US4470133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit having a decoder
Assignee: Fujitsu Ltd
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Filing: 1981-12-16
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Granted: 1984-09-04
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Expires: 2001-12-16
Abstract
Abstract A memory circuit has a decoder circuit for receiving address signals and generating word designating signals. The decoder circuit has a plurality of decoder circuit blocks and includes a circuit for receiving some of the address signals and generating signals designating one of the decoder circuit blocks, whereby the current flowing in each of the decoder circuit blocks is reduced as long as the blocks are not designated.
Inventors
- 👤 Kazuo Tanimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:14
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
162 words
A memory circuit operatively connected to receive address signals and operatively connectable to a voltage source, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells located at the intersections of said word lines and said bit lines; a decoder having a plurality of blocks, for selecting one of said word lines or said bit lines, each of said plurality of blocks including a plurality of decoder circuits, each of said decoder circuits comprising: a plurality of MOS transistors, connected in parallel to each other and connected to the voltage source, having gates, respectively, operatively connected to receive one of the address signals; and switching means, operatively connected to said MOS transistors, for selectively connecting said MOS transistors to the voltage source; and signal generating means, operatively connected to said switching means, for generating a block selecting signal and providing the block selecting signal to said switching means so as to select one of said blocks.
Claim 2
Dependent Claim
162 words
A memory circuit operatively connected to receive address signals and operatively connectable to a voltage source, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells located at the intersections of said word lines and said bit lines; a decoder having a plurality of blocks, for selecting one of said word lines or said bit lines, each of said plurality of blocks including a plurality of decoder circuits, each of said decoder circuits comprising: a plurality of MOS transistors, connected in parallel to each other and connected to the voltage source, having gates, respectively, operatively connected to receive one of the address signals; and switching means, operatively connected to said MOS transistors, for selectively connecting said MOS transistors to the voltage source; and signal generating means, operatively connected to said switching means, for generating a block selecting signal and providing the block selecting signal to said switching means so as to select one of said blocks.
Claim 3
Dependent Claim
22 words
A memory circuit according to claim 1, wherein said plurality of MOS transistors in each of said decoder circuits form NAND gates.
Claim 4
Dependent Claim
137 words
A memory circuit operatively connected to receive address signals, each of the address signals including a plurality of bits and having a first portion and a second portion, said memory circuit comprising: a memory array having word lines; a decoder operatively connected to said word lines and divided into blocks of decoder circuits, each of said blocks of decoder circuits receiving the first portion of one of the address signals and each of said blocks of decoder circuits capable of decoding the first portion of one of the address signals and activating one of the word lines; and a block selection circuit, operatively connected to said blocks of decoder circuits and operatively connected to receive the second portion of said one of the address signals, for activating one of said blocks of decoder circuits in said decoder.
Claim 5
Dependent Claim
137 words
A memory circuit operatively connected to receive address signals, each of the address signals including a plurality of bits and having a first portion and a second portion, said memory circuit comprising: a memory array having word lines; a decoder operatively connected to said word lines and divided into blocks of decoder circuits, each of said blocks of decoder circuits receiving the first portion of one of the address signals and each of said blocks of decoder circuits capable of decoding the first portion of one of the address signals and activating one of the word lines; and a block selection circuit, operatively connected to said blocks of decoder circuits and operatively connected to receive the second portion of said one of the address signals, for activating one of said blocks of decoder circuits in said decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-04 | 1988-03-05 | 1988-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-04 | 1992-03-05 | 1992-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-04 | 1996-03-05 | 1996-09-04 | $7700.00 | Window Closed / Lapsed |