Half good chip with low power dissipation

Claim 1

For use in a monolithic memory: a chip containing at least one first array of memory cells which will be utilized for storage of information in said memory and at least one second array of memory cells which will not be utilized for storage of information in said memory; a source of voltage connectable to said first array for controlling the application of power thereto; addressing means for designating corresponding memory cells in said first and second arrays, said addressing means comprising word decoding means associated with both said first array and said second array, first bit decoding means associated with said first array, and second bit decoding means associated with said second array; array selection means capable of selecting said first array for causing said address designation to be transmitted to said first array; first gating means comprising first FET switch means connected between said word decoding means and said first array, and second FET switch means connected between said first bit decoding means and said second array; and second gating means comprising third FET switch means connected between said word decoding means and said second array, and fourth FET switch means connected between said second bit decoding means and said second array; all of said switch means being controlled by said array selection means; whereby, when said chip is used in said monolithic memory, power and address signals may be transmitted to said first array without being transmitted to said second array.