Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics

Claim 2

An inverter circuit, comprising: a low-potential power supply; a first high-potential power supply; a second high-potential power supply, the potential of said second high-potential power supply being higher than that of said first high-potential power supply; clock signal generating means, operatively connected to said first high-potential power supply, for generating first and second clock signals approximately opposite in phase; a load MIS transistor and a driving MIS transistor operatively connected in series between said low-potential power supply and said second high-potential power supply, said load MIS transistor and said driving MIS transistor each having a gate for receiving a respective one of said clock signals; a connection node, formed between said load MIS transistor and said driving MIS transistor, for outputting an output signal; at least one first MIS transistor, operatively connected between said second high-potential power supply and said load MIS transistor, having a gate; and means, operatively connected to said first high-potential power supply and said gate of said first MIS transistor, for raising a gate potential of said first MIS transistor to a potential level higher than that of said second high-potential power supply.

Claim 3

An inverter circuit as set forth in claim 1, wherein said means for raising the gate potential comprises: a second MIS transistor having a drain and a gate commonly connected to said first high-potential power supply and having a source operatively connected to the gate of said first MIS transistor; and a capacitor having a first electrode operatively connected to said source of said second MIS transistor and having a second electrode operatively connected to said connection mode.

Claim 4

An inverter circuit being operatively connectable to a low-potential power supply, first and second high-potential power supplies and clock signal generating means for generating first and second clock signals approximately opposite in phase, the potential of the second high-potential power supply being higher than that of the first high-potential power supply, said inverter circuit comprising: a load transistor, operatively connected to the clock signal generating means and the second high-potential power supply, having a gate for receiving the first clock signal; a driving transistor, operatively connected to said load transistor, the low-potential power supply and the clock signal generating means, having a gate for receiving the second clock signal; a first transistor having a gate, operatively connected between said load transistor and the second high-potential power supply, for reducing the load on said load transistor; a second transistor, operatively connected between said load transistor and said driving transistor and operatively connected to the second high-potential power supply, forming a connection node between said second transistor and said load transistor and for reducing the load on said driving transistor; and raising means, operatively connected to the first high-potential power supply and the gate of said first transistor, for raising the potential on the gate of said first transistor to a potential level higher than that on the gate of the second high-potential power supply.

Claim 5

An inverter circuit being operatively connectable to a low-potential power supply, first and second high-potential power supplies and clock signal generating means for generating first and second clock signals approximately opposite in phase, the potential of the second high-potential power supply being higher than that of the first high-potential power supply, said inverter circuit comprising: a load transistor, operatively connected to the clock signal generating means and the second high-potential power supply, having a gate for receiving the first clock signal; a driving transistor, operatively connected to said load transistor, the low-potential power supply and the clock signal generating means, having a gate for receiving the second clock signal; a first transistor having a gate, operatively connected between said load transistor and the second high-potential power supply, for reducing the load on said load transistor; a second transistor, operatively connected between said load transistor and said driving transistor and operatively connected to the second high-potential power supply, forming a connection node between said second transistor and said load transistor and for reducing the load on said driving transistor; and raising means, operatively connected to the first high-potential power supply and the gate of said first transistor, for raising the potential on the gate of said first transistor to a potential level higher than that on the gate of the second high-potential power supply.

Claim 6

An inverter circuit as set forth in claim 3, wherein said raising means comprises: a third transistor operatively connected to the first high-potential power supply and said first transistor; and a capacitor having a first electrode operatively connected to said third transistor and having a second electrode operatively connected to the connection node.

Claim 7

An inverter circuit, comprising: a low-potential power supply; a first high-potential power supply; a second high-potential power supply, the potential of said second high-potential power supply being higher than that of said first high-potential power supply; clock signal generating means, operatively connected to said first high-potential power supply, for generating first and second clock signals approximately opposite in phase; a load MIS transistor and a driving MIS transistor operatively connected in series between said low-potential power supply and said second high-potential power supply, said load MIS transistor and said driving MIS transistor each having a gate for receiving a respective one of said clock signals; a connection node, formed between said load MIS transistor and said driving MIS transistor, for outputting an output signal; at least one first MIS transistor, operatively connected between said second high-potential power supply and said load MIS transistor, having a gate; and means, operatively connected to said first high-potential power supply and the gate of said first MIS transistor, for raising a gate potential of said first MIS transistor to a potential level higher than that of said second high-potential power supply, said means comprising: a second MIS transistor having a drain and a gate commonly connected to said first high-potential power supply and having a source operatively connected to the gate of said first MIS transistor; and a capacitor having a first electrode operatively connected to the source of said second MIS transistor and to the gate of said first MIS transistor and having a second electrode operatively connected to the gate of said load MIS transistor.

Claim 8

An inverter circuit, comprising: a low-potential power supply; a first high-potential power supply; a second high-potential power supply, the potential of said second high-potential power supply being higher than that of said first high-potential power supply; clock signal generating means, operatively connected to said first high-potential power supply, for generating first and second clock signals approximately opposite in phase; a load MIS transistor and a driving MIS transistor operatively connected in series between said low-potential power supply and said second high-potential power supply, said load MIS transistor and said driving MIS transistor each having a gate for receiving a respective one of said clock signals; a connection node, formed between said load MIS transistor and said driving MIS transistor, for outputting an output signal; at least one first MIS transistor, operatively connected between said second high-potential power supply and said load MIS transistor, having a gate; and means, operatively connected to said first high-potential power supply and the gate of said first MIS transistor, for raising a gate potential of said first MIS transistor to a potential level higher than that of said second high-potential power supply, said means comprising: a second MIS transistor having a drain and a gate commonly connected to said first high-potential power supply and having a source operatively connected to the gate of said first MIS transistor; and a capacitor having a first electrode operatively connected to the source of said second MIS transistor and to the gate of said first MIS transistor and having a second electrode operatively connected to the gate of said load MIS transistor.

Claim 9

An inverter circuit being operatively connectable to a low-potential power supply, first and second high-potential power supplies and clock signal generating means for generating first and second clock signals approximately opposite in phase, the potential of the second high-potential power supply being higher than that of the first high-potential power supply, said inverter circuit comprising: a load transistor, operatively connected to the clock signal generating means and the second high-potential power supply, having a gate for receiving the first clock signal; a driving transistor, operatively connected to said load transistor, the low-potential power supply and the clock signal generating means, having a gate for receiving the second clock signal; a first transistor having a gate, operatively connected between said load transistor and the second high-potential power supply, for reducing the load on said load transistor; a second transistor, operatively connected between said load transistor and said driving transistor and operatively connected to the second high-potential power supply, forming a connection node between said second transistor and said load transistor and for reducing the load on said driving transistor; and raising means, operatively connected to the first high-potential power supply and the gate of said first transistor, for raising the potential of said first transistor to a potential level higher than that of the second high-potential power supply, said raising means comprising: a third transistor operatively connected to the first high-potential power supply and said first transistor; and a capacitor having a first electrode operatively connected to said third transistor and to the gate of said first transistor and having a second electrode operatively connected to the gate of said load transistor.

Claim 10

An inverter circuit being operatively connectable to a low-potential power supply, first and second high-potential power supplies and clock signal generating means for generating first and second clock signals approximately opposite in phase, the potential of the second high-potential power supply being higher than that of the first high-potential power supply, said inverter circuit comprising: a load transistor, operatively connected to the clock signal generating means and the second high-potential power supply, having a gate for receiving the first clock signal; a driving transistor, operatively connected to said load transistor, the low-potential power supply and the clock signal generating means, having a gate for receiving the second clock signal; a first transistor having a gate, operatively connected between said load transistor and the second high-potential power supply, for reducing the load on said load transistor; a second transistor, operatively connected between said load transistor and said driving transistor and operatively connected to the second high-potential power supply, forming a connection node between said second transistor and said load transistor and for reducing the load on said driving transistor; and raising means, operatively connected to the first high-potential power supply and the gate of said first transistor, for raising the potential of said first transistor to a potential level higher than that of the second high-potential power supply, said raising means comprising: a third transistor operatively connected to the first high-potential power supply and said first transistor; and a capacitor having a first electrode operatively connected to said third transistor and to the gate of said first transistor and having a second electrode operatively connected to the gate of said load transistor.