One-chip microcomputer

Claim 2

A one-chip microcomputer having a direct memory access and central processing unit operation mode, comprising: a central processing unit having arithmetic, logic and control units, for setting the direct memory access operation mode or central processing unit operation mode and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data in a predetermined area and instructions processed by said central processing unit; an output buffer register, operatively connected to said central processing unit, for storing the first data processed by said central processing unit; a direct memory access controller, operatively connected to and controlled by said central processing unit, for reading out the second data from the predetermined area of said random-access memory; port means, operatively connected to said output buffer and said random access memory, for receiving the first data from said output buffer register and the second data, from said random-access memory; terminals operatively connected to said port means and used for the central processing unit operation mode and the direct memory access operation mode; and time-division means, operatively connected to said direct memory access controller and said port means and controlled by said direct memory access controller, for transmitting the first and second data through said port means to said terminals.

Claim 3

A one-chip microcomputer as set forth in claim 1, further comprising an address counter, operatively connected to said direct memory access controller and said random access memory and controlled by said direct memory access controller, for generating an address signal to read the second data from the predetermined area of said random-access memory.

Claim 4

A one-chip microcomputer having a direct memory access and central processing unit mode, comprising: a central processing unit having arithmetic, logic and control units, for setting the direct memory access operation mode or central processing unit operation mode, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data in a predetermined area and instructions processed by said central processing unit; an output buffer register, operatively connected to said central processing unit and said random access memory, for storing the first data processed by said central processing unit; a direct memory access controller operatively connected to and controlled by said central processing unit; gate means, operatively connected to said random access memory and said central processing unit, for passing signals therethrough and controlled by said central processing unit; address port means, operatively connected to said gate means, for transmitting an externally applied address signal to said random-access memory through said gate means to read the second data from said random-access memory; port means, operatively connected to said output buffer register and said random access memory, for receiving the first data from said output buffer register and the second data from said random-access memory read under the control of said address port means; terminals operatively connected to said port means and used for the central processing unit operation mode and the direct memory access operation mode; and time-division means, operatively connected to said direct memory access controller and said port means and controlled by said direct memory access controller, for transmitting the first and second data through said port means to said terminals.

Claim 5

A one-chip microcomputer having a direct memory access and central processing unit mode, comprising: a central processing unit having arithmetic, logic and control units, for setting the direct memory access operation mode or central processing unit operation mode, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data in a predetermined area and instructions processed by said central processing unit; an output buffer register, operatively connected to said central processing unit and said random access memory, for storing the first data processed by said central processing unit; a direct memory access controller operatively connected to and controlled by said central processing unit; gate means, operatively connected to said random access memory and said central processing unit, for passing signals therethrough and controlled by said central processing unit; address port means, operatively connected to said gate means, for transmitting an externally applied address signal to said random-access memory through said gate means to read the second data from said random-access memory; port means, operatively connected to said output buffer register and said random access memory, for receiving the first data from said output buffer register and the second data from said random-access memory read under the control of said address port means; terminals operatively connected to said port means and used for the central processing unit operation mode and the direct memory access operation mode; and time-division means, operatively connected to said direct memory access controller and said port means and controlled by said direct memory access controller, for transmitting the first and second data through said port means to said terminals.

Claim 6

A microcomputer as set forth in claim 3, wherein said port means comprises bidirectional input/output ports, operatively connected to said random access memory and said output buffer register, through which an externally applied data signal is written into an area of said random-access memory accessed under the control of said address port means.

Claim 7

A one-chip microcomputer, having a central processing unit and direct memory access mode, comprising: a central processing unit having arithmetic, logic and control units for setting the direct memory access or central processing unit operation mode, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data in a predetermined area and instructions processed by said central processing unit; a register, operatively connected to said random access memory and said central processing unit, for storing the same data as that in said predetermined area of said random-access memory, a write operation upon said register and said predetermined area of said random-access memory being simultaneously performed by said central processing unit; direct memory access controller operatively connected to said central processing unit and said register and controlled by said central processing unit; parallel-serial converter means, operatively connected to said central processing unit, said random access memory and said direct memory access controller, and controlled by said central processing unit, for converting parallel data into serial data, said parallel data being sent from said register by said direct memory access controller; and a terminal operatively connected to said parallel-serial converter means and used for the central processing unit operation mode and the direct memory access operation mode.

Claim 8

A one-chip microcomputer, having a central processing unit and direct memory access mode, comprising: a central processing unit having arithmetic, logic and control units for setting the direct memory access or central processing unit operation mode, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data in a predetermined area and instructions processed by said central processing unit; a register, operatively connected to said random access memory and said central processing unit, for storing the same data as that in said predetermined area of said random-access memory, a write operation upon said register and said predetermined area of said random-access memory being simultaneously performed by said central processing unit; direct memory access controller operatively connected to said central processing unit and said register and controlled by said central processing unit; parallel-serial converter means, operatively connected to said central processing unit, said random access memory and said direct memory access controller, and controlled by said central processing unit, for converting parallel data into serial data, said parallel data being sent from said register by said direct memory access controller; and a terminal operatively connected to said parallel-serial converter means and used for the central processing unit operation mode and the direct memory access operation mode.

Claim 9

A one-chip microcomputer as set forth in claim 5, wherein said parallel-serial converter means comprises: a shift register, operatively connected to said register and said direct memory access controller, for receiving parallel data from said register; and a serial input/output circuit, operatively connected to said central processing unit, said shift register, and said random access memory, and controlled by said central processing unit, for performing a shift operation upon said shift register.

Claim 10

A one-chip microcomputer as set forth in claim 5, wherein the predetermined area of said random-access memory comprises at least one predetermined bit of predetermined data words.

Claim 11

A one-chip microcomputer having a central processing unit and data memory access operation mode, comprising: a central processing unit having arithmetic, logic and control units for setting direct memory access or central processing unit operation modes, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data and instructions processed by said central processing unit; a direct memory access controller operatively connected to and controlled by said central processing unit; an address counter, operatively connected to said random access memory and said direct memory access controller and controlled by said direct memory access controller for generating an address signal for said random-access memory; parallel-serial converter means, operatively connected to said central processing unit and said random access memory, and controlled by said central processing unit, for converting parallel data into serial data, the data of said random-access memory accessed under the control of said address counter being input into said parallel-serial converter means; and a terminal operatively connected to said parallel-serial converter means and used for the central processing unit operation mode and direct memory access operation mode.

Claim 12

A one-chip microcomputer having a central processing unit and data memory access operation mode, comprising: a central processing unit having arithmetic, logic and control units for setting direct memory access or central processing unit operation modes, and for processing first and second data; a random-access memory, operatively connected to said central processing unit, for storing the second data and instructions processed by said central processing unit; a direct memory access controller operatively connected to and controlled by said central processing unit; an address counter, operatively connected to said random access memory and said direct memory access controller and controlled by said direct memory access controller for generating an address signal for said random-access memory; parallel-serial converter means, operatively connected to said central processing unit and said random access memory, and controlled by said central processing unit, for converting parallel data into serial data, the data of said random-access memory accessed under the control of said address counter being input into said parallel-serial converter means; and a terminal operatively connected to said parallel-serial converter means and used for the central processing unit operation mode and direct memory access operation mode.

Claim 13

A one-chip microcomputer as set forth in claim 8, wherein said parallel-serial converter means comprises: a shift register operatively connected to said random access memory and said central processing unit, for receiving parallel data from said random-access memory; and a serial input/output circuit, operatively connected to said shift register, said central processing unit, and said random access memory and controlled by said central processing unit, for performing a shift operation on said shift register.

Claim 14

A one-chip microcomputer as set forth in claim 3, further comprising flip-flops, operatively connected to said time division means and said terminals, for providing a permission signal to permit the direct memory access operation mode.

Claim 15

A one-chip microcomputer as set forth in claim 1, wherein said port means comprises input/output ports, operatively connected to the respective said terminals, said random access memory and said output buffer, each port means comprising: two AND gates each operatively connected to said output buffer and said random access memory; and an OR gate operatively connected between said two AND gates and the respective said terminal.

Claim 16

A one-chip microcomputer as set forth in claim 1, wherein said time division means comprises inverters operatively connected to said port means and said direct memory access controller.