Three state input circuits

Claim 2

A three state input circuit comprising: a first load means having two terminals, one of which is coupled to a first fixed potential source; a first switch means coupled between a signal input terminal and the other terminal of said first load means and controlled by a second timing signal; a second load means having two terminals, one of which is coupled to a second fixed potential source; a second switch means coupled between said signal input terminal and the other terminal of said second load means and controlled by a first timing signal; a first memory means controlled by a fourth timing signal for selectively storing a first signal potential level of said other terminal of said first load means so as to output said signal potential level to a first signal output terminal; and a second memory means controlled by a third timing signal for selectively storing a second signal potential level of said other terminal of said second load means so as to output said second signal potential level to a second signal output terminal; wherein said circuit sequentially and periodically operates such that in response to said first and second timing signals, said circuit sequentially and periodically closes one of said first and second previously open switch means, then opens said one switch means, then closes the other of said first and second switch means, then opens said other switch means.

Claim 3

A three state input circuit comprising: a first load means having two terminals, one of which is coupled to a first fixed potential source; a first switch means coupled between a signal input terminal and the other terminal of said first load means and controlled by a second timing signal; a second load means having two terminals, one of which is coupled to a second fixed potential source; a second switch means coupled between said signal input terminal and the other terminal of said second load means and controlled by a first timing signal; a first memory means controlled by a fourth timing signal for selectively storing a first signal potential level of said other terminal of said first load means so as to output said signal potential level to a first signal output terminal; and a second memory means controlled by a third timing signal for selectively storing a second signal potential level of said other terminal of said second load means so as to output said second signal potential level to a second signal output terminal; wherein said circuit sequentially and periodically operates, in response to said first and second timing signals, such that it first closes one of said switch means and opens the other of said previously closed switch means and then closes said one open switch means and leaves closed said other switch means.

Claim 4

A three state input circuit comprising: a first load means having two terminals, one of which is coupled to a first fixed potential source; a first switch means coupled between a signal input terminal and the other terminal of said first load means and controlled by a second timing signal; a second load means having two terminals, one of which is coupled to a second fixed potential source; a second switch means coupled between said signal input terminal and the other terminal of said second load means and controlled by a first timing signal; a first memory means controlled by a fourth timing signal for selectively storing a first signal potential level of said other terminal of said first load means so as to output said signal potential level to a first signal output terminal; and a second memory means controlled by a third timing signal for selectively storing a second signal potential level of said other terminal of said second load means so as to output said second signal potential level to a second signal output terminal; wherein said circuit sequentially and periodically operates, in response to said first and second timing signals, such that it first closes one of said switch means and opens the other of said previously closed switch means and then closes said one open switch means and leaves closed said other switch means.

Claim 5

A three state input circuit comprising: a high and a low fixed potential source; a signal input terminal for receiving a three-state signal having a low level, a high level, and an open floating level; first and second output terminals; a first load means having two terminals, one of which is coupled to said high fixed potential source; a second load means having two terminals, one of which is coupled to said low fixed potential source; an N-channel MOSFET having a source electrode coupled to the other terminal of said first load means, a drain electrode coupled to said signal input terminal, and a gate electrode connected to receive a second timing signal; a P-channel MOSFET having a drain electrode coupled to said signal input terminal, a source electrode coupled to the other terminal of said second load means, and a gate electrode connected to receive a first timing signal which has the same period as said second timing signal and is out of phase with said first timing signal; a first memory means for temporarily storing a signal potential level of said source electrode of said N-channel MOSFET in accordance with a fourth timing signal which is received during the presence of said second timing signal and for sending one bit of a two-bit binary signal corresponding to said input signal to said first output terminal; and a second memory means for temporarily storing a signal potential level of said source electrode of said P-channel MOSFET by a third timing signal which is received during the presence of said first timing signal and for sending the other bit of said binary signal to said second terminal; whereby said N- and P-channel MOSFETs operate so as not to change their conduction states at the same time.

Claim 6

A three state input circuit comprising: a high and a low fixed potential source; a signal input terminal for receiving a three-state signal having a low level, a high level, and an open floating level; first and second output terminals; a first load means having two terminals, one of which is coupled to said high fixed potential source; a second load means having two terminals, one of which is coupled to said low fixed potential source; an N-channel MOSFET having a source electrode coupled to the other terminal of said first load means, a drain electrode coupled to said signal input terminal, and a gate electrode connected to receive a second timing signal; a P-channel MOSFET having a drain electrode coupled to said signal input terminal, a source electrode coupled to the other terminal of said second load means, and a gate electrode connected to receive a first timing signal which has the same period as said second timing signal and is out of phase with said first timing signal; a first memory means for temporarily storing a signal potential level of said source electrode of said N-channel MOSFET in accordance with a fourth timing signal which is received during the presence of said second timing signal and for sending one bit of a two-bit binary signal corresponding to said input signal to said first output terminal; and a second memory means for temporarily storing a signal potential level of said source electrode of said P-channel MOSFET by a third timing signal which is received during the presence of said first timing signal and for sending the other bit of said binary signal to said second terminal; whereby said N- and P-channel MOSFETs operate so as not to change their conduction states at the same time.

Claim 7

A three state input circuit according to claim 3, wherein said first memory means comprises a first data flip-flop circuit which comprises CMOS gates, and said second memory means comprises a second data flip-flop circuit which comprises CMOS gates.

Claim 8

A three state input circuit according to claim 3, further comprising a second P-channel MOSFET connected in parallel to said N-channel MOSFET so as to operate as a CMOS analogue switch and controlled by said second timing signal, and a second N-channel MOSFET connected in parallel to said P-channel MOSFET so as to operate as a CMOS analogue switch and controlled by said first timing signal.

Claim 9

A three state input circuit according to claim 5, wherein said first memory means comprises a first data flip-flop circuit which comprises CMOS gates, and said second memory means comprises a second data flip-flop circuit which comprises CMOS gates.

Claim 10

A three state input circuit comprising: a high and a low fixed potential source; a signal input terminal for receiving a three-state signal having a low level, a high level, and an open floating level; first and second output terminals; a first load means having two terminals, one of which is coupled to said high fixed potential source; a second load means having two terminals, one of which is coupled to said low fixed potential source; an N-channel MOSFET having a source electrode coupled to the other terminal of said first load means, a drain electrode coupled to said signal input terminal, and a gate electrode connected to receive a second timing signal; a P-channel MOSFET having a drain electrode coupled to said signal input terminal, a source electrode coupled to the other terminal of said second load means, and a gate electrode connected to receive a first timing signal which has the same period as said first timing signal and is out of phase with said first timing signal; a first memory means for temporarily storing a signal potential level of said source electrode of said N-channel MOSFET in accordance with said second timing signal and for sending one bit of a two-bit binary signal corresponding to said input signal to said first output terminal; and a second memory means for temporarily storing a signal potential level of said source electrode of said P-channel MOSFET in accordance with said first timing signal and sending the other bit of said binary signal to said second output terminal; whereby said N- and P-channel MOSFETs operate so as not to turn ON and OFF at the same time.

Claim 11

A three state input circuit comprising: a high and a low fixed potential source; a signal input terminal for receiving a three-state signal having a low level, a high level, and an open floating level; first and second output terminals; a first load means having two terminals, one of which is coupled to said high fixed potential source; a second load means having two terminals, one of which is coupled to said low fixed potential source; an N-channel MOSFET having a source electrode coupled to the other terminal of said first load means, a drain electrode coupled to said signal input terminal, and a gate electrode connected to receive a second timing signal; a P-channel MOSFET having a drain electrode coupled to said signal input terminal, a source electrode coupled to the other terminal of said second load means, and a gate electrode connected to receive a first timing signal which has the same period as said first timing signal and is out of phase with said first timing signal; a first memory means for temporarily storing a signal potential level of said source electrode of said N-channel MOSFET in accordance with said second timing signal and for sending one bit of a two-bit binary signal corresponding to said input signal to said first output terminal; and a second memory means for temporarily storing a signal potential level of said source electrode of said P-channel MOSFET in accordance with said first timing signal and sending the other bit of said binary signal to said second output terminal; whereby said N- and P-channel MOSFETs operate so as not to turn ON and OFF at the same time.

Claim 12

A three state input circuit according to claim 7, wherein said first memory means comprises a first data flip-flop circuit which comprises CMOS gates, and said second memory means comprises a second data flip-flop circuit which comprises CMOS gates.

Claim 13

A three state input circuit according to claim 7, further comprising a second P-channel MOSFET connected in parallel said N-channel MOSFET so as to operate as a CMOS analogue switch and controlled by said second timing signal, and a second N-channel MOSFET connected in parallel to said P-channel MOSFET so as to operate as a CMOS analogue switch and controlled by said first timing signal.

Claim 14

A three state input circuit according to claim 9, wherein said first memory means comprises a first data flip-flop circuit which comprises CMOS gates, and said second memory means comprises a second data flip-flop circuit which comprises CMOS gates.