US4163907A
Expired / Lapsed
US
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Three logic state input buffers
Assignee: Harris Corp
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Filing: 1977-09-16
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Granted: 1979-08-07
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Expires: 1997-09-16
Abstract
Abstract A buffer having a single input and a pair of outputs providing three unambiguous logic output states including a first output connected directly to the input and a second output connected to the junction of a common gate configured FET and an impedance. The input is also connected to the source and body of the FET and a voltage source is connected to the impedance. The first output varies with the input for a first polarity input signal and the second output varies with the input for the opposite polarity input signal.
Inventors
- 👤 James E. Schroeder
- 👤 Richard L. Goslin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
86 words
A three logic state buffer comprising: input means for receiving positive and negative polarity input signals; first output means for providing two logic level output signals for one polarity of said input signals; semiconductor switch means connected to said input means; impedance means connected between a voltage source and said switch means; and second output means connected to the junction of said switch means and said impedance means for providing two logic level output signals for a polarity of said input signals opposite said one polarity.
Claim 2
Dependent Claim
86 words
A three logic state buffer comprising: input means for receiving positive and negative polarity input signals; first output means for providing two logic level output signals for one polarity of said input signals; semiconductor switch means connected to said input means; impedance means connected between a voltage source and said switch means; and second output means connected to the junction of said switch means and said impedance means for providing two logic level output signals for a polarity of said input signals opposite said one polarity.
Claim 3
Dependent Claim
49 words
The three logic state buffer according to claim 1 wherein said switch means presents an electrical impedance to said input signal, said switch means and impedance means are ratioed so that said second output means is capable of operating with a voltage source variation of four to eleven volts.
Claim 4
Dependent Claim
25 words
The three logic state buffer according to claim 1 wherein said switching means includes an enhancement mode field effect transistor in a common gate configuration.
Claim 5
Dependent Claim
36 words
The three logic state buffer according to claim 3 wherein said input means applies said input signals to the source and body of said field effect transistor and said gate is connected to a fixed potential.
Claim 6
Dependent Claim
31 words
The three logic state buffer according to claim 4 wherein said field effect transistor is an N channel insulated gate field effect transistor and said voltage source is of positive polarity.
Claim 7
Dependent Claim
16 words
The three logic state buffer according to claim 3 wherein said impedance means includes a resistor.
Claim 8
Dependent Claim
17 words
The three state buffer according to claim 1 wherein said input means is a single input terminal.
Claim 9
Dependent Claim
32 words
The three state buffer according to claim 1 wherein said first output means is responsive to positive polarity input signals and said second output means is responsive to negative polarity input signals.
Claim 10
Dependent Claim
29 words
The three state buffer according to claim 8 wherein said first and second output means provide a fixed logic level output signal for negative and positive input signals, respectively.
Claim 11
Dependent Claim
96 words
A logic buffer comprising: a voltage source terminal; a signal input terminal; a first output means connected directly to said input terminal; a second output means; an impedance connected between said voltage source terminal and said second output means; and a field effect transistor having a gate connected to a fixed potential, a drain connected to said second output means and a source and body connected to said signal input terminal whereby positive and negative input signals at said signal input terminal results in distinct level signals being produced by said first and second output means.
Claim 12
Dependent Claim
96 words
A logic buffer comprising: a voltage source terminal; a signal input terminal; a first output means connected directly to said input terminal; a second output means; an impedance connected between said voltage source terminal and said second output means; and a field effect transistor having a gate connected to a fixed potential, a drain connected to said second output means and a source and body connected to said signal input terminal whereby positive and negative input signals at said signal input terminal results in distinct level signals being produced by said first and second output means.
Claim 13
Dependent Claim
46 words
The logic buffer according to claim 10 wherein said field effect transistor is an enhancement mode device whereby said first output terminal assumes two logic states for input signals of one polarity and said second output assumes two logic states for input signals of opposite polarity.
Claim 14
Dependent Claim
37 words
The logic buffer according to claim 10 wherein said field effect transistor is a depletion mode device whereby said first and second outputs each assume two logic states at different values of input signals of one polarity.
Claim 15
Dependent Claim
13 words
The logic buffer according to claim 10 wherein said impedance is a resistor.
Claim 16
Dependent Claim
15 words
The logic buffer according to claim 10 wherein said impedance is a field effect transistor.
Claim 17
Dependent Claim
21 words
The logic buffer according to claim 10 wherein said voltage source may be in the range of four to eleven volts.
Claim 18
Dependent Claim
102 words
A three logic state input buffer for FET logic comprising: input means for receiving positive and negative input signals; first output means connected to said input means for providing two FET compatible logic state signals in response to said input signals of a first polarity; and second output means connected to said input means for providing two FET compatible logic state signals in response to an input signal of a polarity opposite said first polarity said second output means including a common gate configuration FET connected to said input means and an impedance connected to said FET and a positive reference voltage.
Claim 19
Dependent Claim
102 words
A three logic state input buffer for FET logic comprising: input means for receiving positive and negative input signals; first output means connected to said input means for providing two FET compatible logic state signals in response to said input signals of a first polarity; and second output means connected to said input means for providing two FET compatible logic state signals in response to an input signal of a polarity opposite said first polarity said second output means including a common gate configuration FET connected to said input means and an impedance connected to said FET and a positive reference voltage.
Claim 20
Dependent Claim
36 words
The buffer according to claim 16 wherein said first output means provides said logic signals in response to positive input signals and said second output means provides said logic signals in response to negative input signals.
Claim 21
Dependent Claim
50 words
The buffer according to claim 16 wherein said input means is connected to the body and source of said FET and the impedance of said FET and said impedance are ratioed so as to be capable of operating with a reference voltage in the range of four to eleven volts.
Claim 22
Dependent Claim
46 words
The buffer according to claim 16 wherein said first output means provides a fixed logic state signal in response to input signals of said opposite polarity and said second output means provides a fixed logic state signal in response to input signals of said first polarity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-06 | 1983-02-05 | 1983-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-06 | 1987-02-05 | 1987-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-06 | 1991-02-05 | 1991-08-07 | $7700.00 | Window Closed / Lapsed |