Apparatus for fetching and decoding instructions

Claim 2

A digital computer system for processing data comprising: memory means for storing and providing said data including instructions in response to memory input signals, said memory means including input bus means for conducting said data and said memory input signals to said memory means and output bus means for conducting said data from said memory means; and processor means responsive to said instructions for receiving said data from said memory means, processing said data, and providing said data and said memory input signals to said memory means, said processor means including pre-fetch means coupled to said input bus means and said output bus means for providing said memory input signals specifying said instructions to said memory means, for receiving said instructions output from said memory means, for storing said received instructions, and for outputting said received instructions, pre-fetch bus means connected to said pre-fetch means for receiving said instructions output by said pre-fetch means, and CPU means coupled to said input bus means and said output bus means for processing said data, said CPU means including instruction interpretation means connected to said pre-fetch bus means for selecting one of said instructions received in said prefetch means, for receiving said selected instruction, and for controlling said CPU means in response to said selected instruction.

Claim 3

The digital computer system of claim 1 wherein said pre-fetch means comprises: means for determining when said CPU means does not require access to said memory means; instruction fetching means responsive to operation of said determining means for providing said memory input signals specifying said instructions to said memory means; pre-fetch memory means for receiving said instructions received from said memory means and for storing said received instructions; and instruction output means responsive to said instruction interpretation means for outputting said selected instruction from said pre-fetch memory means to said pre-fetch bus means when said selected instruction is stored in said pre-fetch memory means.

Claim 4

The digital computer system of claim 2 wherein said pre-fetch means further comprises comparison means responsive to operation of said prefetch means and to operation of said CPU means for indicating availability of said selected instruction in said pre-fetch memory means.

Claim 5

The digital computer system of claim 2 wherein said pre-fetch means further comprises monitoring means responsive to operation of said memory means for indicating possible conflict between a said instruction stored in said pre-fetch means and a corresponding said instruction in said memory means.

Claim 6

The digital computer system of claim 1 wherein said instruction interpretation means comprises: means for receiving certain of said instructions, means for deriving sequences of microinstructions from each of said certain said instructions for said controlling of said CPU in accordance with said certain said instructions and for said selecting of said next one of said instructions, and output means for providing said sequences of microinstructions to said CPU means.

Claim 7

The digital computer system of claim 5 wherein said microinstruction deriving means comprises: microinstruction memory means for storing and providing said sequences of microinstructions, initial decoding means responsive to said certain said instructions for providing initial selection signals to said microinstruction memory means for selecting initial said microinstructions of said sequences of microinstructions, and, microinstruction control means responsive to said stored instructions and responsive to said sequences of microinstructions for providing other selection signals to said microinstruction memory means.

Claim 8

The digital computer system of claim 1 wherein said memory means comprises: memory input means for receiving said memory input signals from said input bus means; a plurality of memory modules, each module of said plurality connected from said input means and capable of performing memory related operations concurrently with and independently of performance by all other modules of said memory related operations; memory logic means connected from said memory input means and deriving memory control signals from said memory input signals for providing said memory control signals to said memory modules; and output multiplexor means for selectively transferring said data and said instructions from said plurality of memory modules to said output bus means.

Claim 9

The digital computer system of claim 1 wherein said memory means outputs said data in response to said memory input signals within a predetermined time interval, and said pre-fetch means further comprises means for generating said memory input signals specifying said instructions, means responsive to operation of said generating means for measuring said predetermined time interval, and means connected from said memory output bus and responsive to operation of said measuring means for receiving said instructions and for storing said instructions.

Claim 10

The digital computer system of claim 1 wherein said data and said instructions are digital machine language signals; and said digital computer system further comprises I/O means for conducting said data and said instructions between said processor means and outside of said system, said I/O means including means for receiving system input signals and for storing representations of said system input signals, means for converting said stored representations of said system input signals into said digital machine language signals, and means for providing said converted digital machine language signals to said CPU means.

Claim 11

In a computer system capable of processing data signals, said system including processor means for processing said data, memory means for storing at least instructions for use by said processor means, memory input bus means for conducting memory input signals from said processor means to said memory means, memory output bus means for conducting memory output signals from said memory means to said processor means, and I/O means for communicating system input signals into said processor means from outside of said system and for communicating system output signals to outside of said system from said processor means, and wherein said processor means includes instruction interpretation means for controlling operation of said processor means and for selecting the next said instruction in response to one of said instructions, instruction pre-fetch means comprising: means responsive to operation of said processor means for determining when said processor means does not require access to said memory means; instruction request means connected to said memory input bus means and responsive to operation of said determining means for generating said memory input signals representing requests for said instructions from said memory means asynchronously to operation of said processor means; pre-fetch memory means for receiving said memory output signals representing said requested instructions, for storing said requested instructions, for outputting a selected one of said requested instructions in response to said instruction interpretation means; and pre-fetch bus means connected from said pre-fetch memory means to said instruction interpretation means and responsive to operation of said processor means for conducting said requested instructions from said pre-fetch memory means to said instruction interpretation means.

Claim 12

In a computer system capable of processing data signals, said system including processor means for processing said data, memory means for storing at least instructions for use by said processor means, memory input bus means for conducting memory input signals from said processor means to said memory means, memory output bus means for conducting memory output signals from said memory means to said processor means, and I/O means for communicating system input signals into said processor means from outside of said system and for communicating system output signals to outside of said system from said processor means, and wherein said processor means includes instruction interpretation means for controlling operation of said processor means and for selecting the next said instruction in response to one of said instructions, instruction pre-fetch means comprising: means responsive to operation of said processor means for determining when said processor means does not require access to said memory means; instruction request means connected to said memory input bus means and responsive to operation of said determining means for generating said memory input signals representing requests for said instructions from said memory means asynchronously to operation of said processor means; pre-fetch memory means for receiving said memory output signals representing said requested instructions, for storing said requested instructions, for outputting a selected one of said requested instructions in response to said instruction interpretation means; and pre-fetch bus means connected from said pre-fetch memory means to said instruction interpretation means and responsive to operation of said processor means for conducting said requested instructions from said pre-fetch memory means to said instruction interpretation means.

Claim 13

The instruction pre-fetch means of claim 10 further comprising comparison means responsive to operation of said pre-fetch means and to operation of said processor means for indicating availability of said requested instructions.

Claim 14

The instruction pre-fetch means of claim 10 further comprising monitoring means responsive to operation of said instruction request means and to operation of said memory means for indicating possible conflict between a said requested instruction in said pre-fetch memory means and a corresponding said instruction in said memory means.

Claim 15

The instruction pre-fetch means of claim 10 wherein: said memory means includes means responsive to each of said memory input signals representing a request for a said instruction for providing said corresponding memory output signals representing said requested instruction within a predetermined time interval; said instruction pre-fetch means further comprises means responsive to operation of said instruction request means for measuring said predetermined time interval; and said pre-fetch memory means includes means responsive to operation of said determining means for receiving and storing said requested instruction.

Claim 16

In a computer system including memory means for storing data including instructions belonging to a set of instructions and processor means connected to said memory means for processing said data in response to said instructions, microinstruction logic means in said processor means for controlling said processor means in response to said instructions, said microinstruction logic means comprising; microinstruction memory means for storing and for providing sequences of microinstructions for controlling said processor means, said sequences corresponding to said instructions in said set of instructions; instruction receiving means for receiving one of said instructions at a time; first decoding means connected to said instruction receiving means for selecting the first said microinstruction of said sequence corresponding to said received instruction in response to said received instruction; second decoding means connected to said instruction receiving means and operating in parallel to and slower than said first decoding means for selecting a further microinstruction of said sequence corresponding to said received instruction in response to said received instruction; and control means responsive to said microinstructions in said corresponding sequence for selecting further said microinstructions of said corresponding sequence.

Claim 17

In a computer system including memory means for storing data including instructions belonging to a set of instructions and processor means connected to said memory means for processing said data in response to said instructions, microinstruction logic means in said processor means for controlling said processor means in response to said instructions, said microinstruction logic means comprising; microinstruction memory means for storing and for providing sequences of microinstructions for controlling said processor means, said sequences corresponding to said instructions in said set of instructions; instruction receiving means for receiving one of said instructions at a time; first decoding means connected to said instruction receiving means for selecting the first said microinstruction of said sequence corresponding to said received instruction in response to said received instruction; second decoding means connected to said instruction receiving means and operating in parallel to and slower than said first decoding means for selecting a further microinstruction of said sequence corresponding to said received instruction in response to said received instruction; and control means responsive to said microinstructions in said corresponding sequence for selecting further said microinstructions of said corresponding sequence.

Claim 18

In the microinstruction logic means of claim 14 and wherein: said set of instructions is a subset of another said set of instructions; said microinstruction memory means contains said sequences of microinstructions corresponding to said instructions in said another set; said second decoding means is further responsive to certain said received instructions which belong to said another set of instructions but do not belong to said set of instructions; and said second decoding means responds to any one of said certain received instructions by selecting said first microinstruction of said sequence corresponding to said one certain received instruction.

Claim 19

In a computer system capable of processing machine-language digital data signals, said system including processor means for processing said data signals, memory means for storing at least machine-language digital instructions for use by said processor means, memory input bus means for conducting memory input signals from said processor means to said memory, memory output bus means for conducting memory output signals from said memory to said processor means, and I/O means connected to said processor means for communicating system input signals including character codes into said processor means from outside of said processor system and for communicating system output signals to outside of said system from said processor means, apparatus in said I/O means for providing sequences of said machine-language digital instructions to said processor means in response to sequences of said character codes comprising: means for receiving said character codes of said system input signals and for storing said character codes; interpreting means connected to said receiving and storing means for receiving sequences of said character codes stored in said receiving and storing means and producing sequences of said machine language digital instructions in response to said received sequences of said character codes; and means connected to said processor means and to said interpreting means for providing said machine-language digital instructions produced by said interpreting means to said processor means.

Claim 20

In a computer system capable of processing machine-language digital data signals, said system including processor means for processing said data signals, memory means for storing at least machine-language digital instructions for use by said processor means, memory input bus means for conducting memory input signals from said processor means to said memory, memory output bus means for conducting memory output signals from said memory to said processor means, and I/O means connected to said processor means for communicating system input signals including character codes into said processor means from outside of said processor system and for communicating system output signals to outside of said system from said processor means, apparatus in said I/O means for providing sequences of said machine-language digital instructions to said processor means in response to sequences of said character codes comprising: means for receiving said character codes of said system input signals and for storing said character codes; interpreting means connected to said receiving and storing means for receiving sequences of said character codes stored in said receiving and storing means and producing sequences of said machine language digital instructions in response to said received sequences of said character codes; and means connected to said processor means and to said interpreting means for providing said machine-language digital instructions produced by said interpreting means to said processor means.

Claim 21

In the apparatus of claim 16, and wherein: said I/O means includes character code providing means for providing said character codes sequentially to said means for receiving and storing said character codes; and said means for receiving and storing said character codes includes conversion means connected to said character code providing means for receiving said character codes from said character code providing means and outputting said character codes in parallel to said interpreting means.

Claim 22

In the apparatus of claim 16, and wherein: said interpreting means includes read-only memory means containing said sequences of machine language digital instructions.

Claim 23

A stored program computer system comprising: processor means and microinstruction logic responsive to instructions from said stored program to provide sequences of microinstructions to said processor means, said microinstruction logic including decoding means for decoding each instruction and storing said decoded instruction, means responsive to said stored decoded instruction and to successive microinstructions in said sequences of microinstructions and including a microinstruction memory for addressing in turn said microinstructions in a corresponding sequence of said sequences of microinstructions corresponding to said stored decoded instruction, and starting address generation means operating in parallel with said decoding means and responsive to first certain ones of said instructions for providing an initial address of said corresponding sequence in advance of the time at which said decoding means are capable of providing said initial address.

Claim 24

A stored program computer system comprising: processor means and microinstruction logic responsive to instructions from said stored program to provide sequences of microinstructions to said processor means, said microinstruction logic including decoding means for decoding each instruction and storing said decoded instruction, means responsive to said stored decoded instruction and to successive microinstructions in said sequences of microinstructions and including a microinstruction memory for addressing in turn said microinstructions in a corresponding sequence of said sequences of microinstructions corresponding to said stored decoded instruction, and starting address generation means operating in parallel with said decoding means and responsive to first certain ones of said instructions for providing an initial address of said corresponding sequence in advance of the time at which said decoding means are capable of providing said initial address.

Claim 25

In the stored program computer system of claim 19, and wherein: said instructions further include second certain instructions other than said first certain instructions; values of certain bits in said instructions determine whether one of said instructions is one of said first certain instructions or one of said second certain instructions; and said starting address generation means responds to said certain bits and provides said starting address only in response to said values of said certain bits specifying said first certain instructions.

Claim 26

In the stored program computer system of claim 19, and wherein: said instructions further include second certain instructions other than said first certain instructions; and said decoded instruction in said decoding means provides said starting address when said instruction is one of said second certain instructions and a subsequent address specifying a subsequent microinstruction in said corresponding microinstruction sequence when said instruction is one of said first certain instructions.

Claim 27

In the stored program computer system of claim 19, and wherein: said decoded instruction in said decoding means provides a subsequent address specifying a subsequent microinstruction in said corresponding microinstruction sequence when said instruction is one of said first certain instructions.