Microprogrammed large-scale integration (LSI) microprocessor

Claim 1

A microprogrammed LSI microprocessor comprising: an instruction register for storing at least an operation code field of a macroinstruction; memory means constituted by a first memory section for storing the contents of a decode table in which are located addresses corresponding to the operation code field read out from the instruction register and a second memory section for storing the contents of microprograms; a data bus; an address bus; a location counter connected to the second memory section of the memory means by means of the data bus for storing the contents of the starting address of a microprogram to be executed and read out from the second memory section in accordance with the decode table stored in the first memory section and for transferring the contents of said starting address to the memory means through the address bus, said operation code field from the instruction register being used to designate said starting address; a microinstruction register connected to the second memory section by means of the data bus for storing a microinstruction read out from the second memory section, said microinstruction having been designated by the contents of the starting address read out from the location counter; decoder means for decoding a microinstruction read out from the microinstruction register; an arithmetic logic unit connected to the microinstruction register for executing a microinstruction read out therefrom; a data selection control circuit connected by means of the address bus between the memory means and the instruction register and between the memory means and the location counter for selectively supplying to the memory means the operation code field from the instruction register or the starting address data of microinstructions from the location counter according to whether the decoder means generates a control signal; and a control signal generating circuit connected to the decoder means, the location counter and the microinstruction register and responsive to a control signal from said decoder means for preventing the contents of the starting address of the microprogram read out from the memory means from being stored into the microinstruction register through the data bus and for supplying a set signal so as to store the contents of the starting address into the location counter and at the same time supplying a signal so as to clear the microinstruction register.