Patent US1869001A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4459494A Expired / Lapsed US ⏱️ 0.0 years remaining

IGFET Schmitt circuit

Assignee: Sanyo Electric Co Ltd
•
Filing: 1982-05-12
•
Granted: 1984-07-10
•
Expires: 2002-05-12
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A Schmitt circuit comprises a series connection of a first, second and third MOS transistors connected between a voltage source and the ground, and a fourth MOS transistor connected between the voltage source and the junction of the second and third MOS transistors. An input voltage is applied to the gates of the second and third MOS transistors. The voltage at the junction of the first and second MOS transistors is applied to the gate of the fourth MOS transistor and is also led out as an output. The Schmitt circuit further comprises a series connection of a sixth and seventh MOS transistors connected between the voltage source and the ground for dividing the source voltage, and a fifth MOS transistor connected between the junction of the sixth and seventh MOS transistors and the junction of the first and second MOS transistors and adapted to be rendered conductive when the potential at the said junction exceeds a predetermined voltage.

Inventors

  • 👤 Hiromitsu Takakura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 20:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 234 words
A Schmitt circuit, comprising: first and second power supply terminals, a series connection of a first, second and third insulated gate field effect transistors connected between said first and second power supply terminals, the drain of said second transistor being connected to the source of said first transistor, the source of said second transistor being connected to the drain of said third transistor, a fourth insulated gate field effect transistor having a drain connected to said first power supply terminal and source connected to the junction of said second and third insulated gate field effect transistors, the gate of said first transistor being connected to its respective drain, an input signal voltage being applied to the gates of said second and third insulated gate field effect transistors, the voltage at the junction of said first and second insulated gate field effect transistors being applied to the gate of said fourth insulated gate field effect transistor and being led out as an output signal voltage, potential dividing means for dividing the potential difference between said first and second potentials and providing said divided potential difference at a divided potential difference point, and a fifth insulated gate field effect transistor connected between said divided potential difference point and the junction of said first and second insulated gate field effect transistors and characterized by being rendered conductive when the potential at said junction exceeds a predetermined potential.
Claim 2
Dependent Claim 234 words
A Schmitt circuit, comprising: first and second power supply terminals, a series connection of a first, second and third insulated gate field effect transistors connected between said first and second power supply terminals, the drain of said second transistor being connected to the source of said first transistor, the source of said second transistor being connected to the drain of said third transistor, a fourth insulated gate field effect transistor having a drain connected to said first power supply terminal and source connected to the junction of said second and third insulated gate field effect transistors, the gate of said first transistor being connected to its respective drain, an input signal voltage being applied to the gates of said second and third insulated gate field effect transistors, the voltage at the junction of said first and second insulated gate field effect transistors being applied to the gate of said fourth insulated gate field effect transistor and being led out as an output signal voltage, potential dividing means for dividing the potential difference between said first and second potentials and providing said divided potential difference at a divided potential difference point, and a fifth insulated gate field effect transistor connected between said divided potential difference point and the junction of said first and second insulated gate field effect transistors and characterized by being rendered conductive when the potential at said junction exceeds a predetermined potential.
Claim 3
Dependent Claim 36 words
A Schmitt circuit in accordance with claim 1, wherein said potential dividing means comprises a series connection of a sixth and seventh insulated gate field effect transistors connected between said first and second power supply terminals.

References Cited (Backward Citations)

US3882331A Cited
US3975649A Cited
US4023122A Cited
US4097772A Cited
US4376251A Cited
US4392066A Cited
US4379974A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-07-10 1988-01-09 1988-07-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-07-10 1992-01-09 1992-07-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-07-10 1996-01-09 1996-07-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag