CMOS Device with ion-implanted channel-stop region and fabrication method therefor

Claim 1

A MOS integrated circuit comprising, in combination: a substrate region of a relatively low doping level of a first conductivity type; a first region of a second conductivity type opposite said first conductivity type in said substrate; a first MOS device comprising a source and a drain of said first conductivity type and a channel region extending between said source and drain, said first MOS device located in said first region of said second conductivity type; a second MOS device comprising a source and a drain of said second conductivity type and a channel region extending between said source and drain, said second MOS device located in said substrate; a further region of said first conductivity type and having higher doping than said substrate but lower doping than the doping concentration in said source or drain region of said first MOS device located in said substrate intermediate said first and said second MOS devices; a second region of said first conductivity type located within said further region of said first conductivity type, said second region of said first conductivity type having the same doping concentration and depth as said source and drain regions of said first MOS device; a first thin oxide region located over said further region and said channel regions; a second oxide region having a larger thickness than said first oxide region located over another portion of said substrate; and conductive means for interconnecting said first and said second MOS devices, said conductive means lying over both said first oxide region over said further region and said second oxide region.