Patent US4455566A successfully refreshed from Google Patents.
US4455566A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Highly integrated semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1980-06-16
•
Granted: 1984-06-19
•
Expires: 2000-06-16
Abstract
Abstract A highly integrated semiconductor memory device of a DMOS type, in which one half of the surface area in each memory cell is used as the drain region and another half is used as the gate electrode. The channel region and the source region are formed under the gate electrode so that, the size required by one memory cell is 4F 2 , where F represents the minimum width of a patterning line.
Inventors
- 👤 Junji Sakurai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:07
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
273 words
A semiconductor memory device including bit lines, word lines and a plurality of charge-storage capacitors operatively connected to corresponding ones of a plurality of MOS transistor memory cells formed on a semiconductor substrate of one conductivity type, each of said MOS memory cells comprising: a first region having an opposite conductivity type with respect to said semiconductor substrate and formed on said semiconductor substrate; a gate-oxide layer formed on said first region except on a window for diffusing impurities therethrough; a gate electrode formed on said gate-oxide layer and operatively connected to a corresponding one of said word lines; a second region having the same conductivity type as said semiconductor substrate and formed under said window by diffusing impurities through said window into said first region, said second region extending to a portion under a part of said gate electrode, and; a third region having the same conductivity type as said first region and formed on said second region by diffusing impurities through said window into said second region, and operatively connected to a corresponding one of said bit lines, said gate electrode covering the surface of said first region and said second region and, separated from said first and second regions by said gate-oxide layer, the junction capacitance between said first region and said second region and the capacitance between said first region and said semiconductor substrate form said charge-storage capacitor, and the size of each of said MOS memory cells being substantially equal to 4 F 2 , where F represents both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines.
Claim 2
Dependent Claim
273 words
A semiconductor memory device including bit lines, word lines and a plurality of charge-storage capacitors operatively connected to corresponding ones of a plurality of MOS transistor memory cells formed on a semiconductor substrate of one conductivity type, each of said MOS memory cells comprising: a first region having an opposite conductivity type with respect to said semiconductor substrate and formed on said semiconductor substrate; a gate-oxide layer formed on said first region except on a window for diffusing impurities therethrough; a gate electrode formed on said gate-oxide layer and operatively connected to a corresponding one of said word lines; a second region having the same conductivity type as said semiconductor substrate and formed under said window by diffusing impurities through said window into said first region, said second region extending to a portion under a part of said gate electrode, and; a third region having the same conductivity type as said first region and formed on said second region by diffusing impurities through said window into said second region, and operatively connected to a corresponding one of said bit lines, said gate electrode covering the surface of said first region and said second region and, separated from said first and second regions by said gate-oxide layer, the junction capacitance between said first region and said second region and the capacitance between said first region and said semiconductor substrate form said charge-storage capacitor, and the size of each of said MOS memory cells being substantially equal to 4 F 2 , where F represents both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines.
Claim 3
Dependent Claim
30 words
A semiconductor memory device as claimed in claim 1 wherein a channel region is to be formed under said gate-oxide layer and between said first region and said third region.
Claim 4
Dependent Claim
30 words
A semiconductor memory device as claimed in claim 1 wherein said first region and said third region respectively constitute a source region and a drain region of said MOS transistor.
Claim 5
Dependent Claim
96 words
A semiconductor memory device as claimed in claim 3 wherein the plurality of said memory cells are arranged in a matrix and connected according to a pattern of rows defining bit lines and columns defining word lines in which said gate electrode of each said memory cell along a given column is connected to a single word line; said drain region of each said memory cell along a given row of said matrix is connected to a single bit line, said source region of each said memory cell in said matrix is connected to a ground.
Claim 6
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 4 wherein said gate electrode of each said memory cell along a given row is connected to a separate word line.
Claim 7
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 1 wherein two adjacent memory cells have symmetric structures.
Claim 8
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 6 wherein said third region is common to two adjacent memory cells.
Claim 9
Dependent Claim
33 words
A semiconductor device according to claim 1, wherein said plurality of said memory cells are changed in pairs such that respective third regions of each of said pairs of memory cells are adjoining.
Claim 10
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 1 wherein all of said memory cells have substantially the same structures.
Claim 11
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 9 wherein said first region is an epitaxial-growth region.
Claim 12
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 10 wherein said second region is formed on said first region.
Claim 13
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 9 wherein said first region is an impurity-diffusion region.
Claim 14
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 12 wherein said second region is formed on said first region.
Claim 15
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 9 wherein said first region is an impurity-diffusion region formed by diffusing impurities through said window.
Claim 16
Dependent Claim
251 words
A semiconductor memory device including bit lines, word lines and a plurality of memory cells formed on a semiconductor substrate of one conductivity type, each of said memory cells comprising: a first region having the same conductivity type as said semiconductor substrate and formed on said semiconductor substrate; a gate-oxide layer formed on said first region except on a window for diffusing impurities therethrough; a gate electrode formed on said gate-oxide layer and operatively connected to a corresponding one of said word lines; a second region having an opposite conductivity type as said semiconductor substrate and formed under said window by diffusing impurities through said window into said first region, said second region extending to a portion under a part of said gate electrode, and; a third region having the same conductivity type as said first region and formed on said second region under said window by diffusing impurities through said window into said second region, and operatively connected to a corresponding one of said bit lines; an isolation region, formed in contact with said gate-oxide layer, for isolating said memory cells from each other, said gate electrode covering the surface of said first region and said second region, and separated from said first and said second regions by said gate-oxide layer, the size of each of said memory cells being substantially equal to 4 F 2 , where F represents both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines.
Claim 17
Dependent Claim
251 words
A semiconductor memory device including bit lines, word lines and a plurality of memory cells formed on a semiconductor substrate of one conductivity type, each of said memory cells comprising: a first region having the same conductivity type as said semiconductor substrate and formed on said semiconductor substrate; a gate-oxide layer formed on said first region except on a window for diffusing impurities therethrough; a gate electrode formed on said gate-oxide layer and operatively connected to a corresponding one of said word lines; a second region having an opposite conductivity type as said semiconductor substrate and formed under said window by diffusing impurities through said window into said first region, said second region extending to a portion under a part of said gate electrode, and; a third region having the same conductivity type as said first region and formed on said second region under said window by diffusing impurities through said window into said second region, and operatively connected to a corresponding one of said bit lines; an isolation region, formed in contact with said gate-oxide layer, for isolating said memory cells from each other, said gate electrode covering the surface of said first region and said second region, and separated from said first and said second regions by said gate-oxide layer, the size of each of said memory cells being substantially equal to 4 F 2 , where F represents both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines.
Claim 18
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 15 wherein said second region is formed on said first region.
Claim 19
Dependent Claim
32 words
A semiconductor memory device as claimed in claim 14 or 15 wherein a channel region is to be formed under said gate-oxide layer and between said first region and said third region.
Claim 20
Dependent Claim
21 words
A semiconductor memory device as claimed in claim 14 or 15 wherein each of said memory cells includes one MOS transistor.
Claim 21
Dependent Claim
30 words
A semiconductor memory device as claimed in claim 17 wherein said first region and said third region respectively constitute a source region and a drain region, of said MOS transistor.
Claim 22
Dependent Claim
94 words
A semiconductor memory device as claimed in claim 19 wherein the plurality of said memory cells are arranged in a matrix and connected according to a pattern of rows defining bit lines and columns defining word lines, in which said drain region of each said memory cell along a given row is connected to a single bit line, said gate electrode of each said memory cell along a given row is connected to a separate word line, and said source region of each said memory cell in said matrix is connected to a ground.
Claim 23
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 20 wherein the drain region of predetermined memory cells are not connected to said bit line.
Claim 24
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 18 wherein said first region is an epitaxial-growth region.
Claim 25
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 18 wherein said first region is an impurity-diffusion region.
Claim 26
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 23 wherein said second region is formed on said first region.
Claim 27
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 18 wherein said first region is an impurity-diffusion region formed by diffusing impurities through said window.
Claim 28
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 25 wherein said second region is formed on said first region.
Claim 29
Dependent Claim
19 words
A semiconductor memory device as claimed in claim 18 wherein each memory cell is a charge-pumping type memory cell.
Claim 30
Dependent Claim
21 words
A semiconductor memory device as claimed in claim 18 wherein the windows of predetermined memory cells are covered with insulating films.
Claim 31
Dependent Claim
17 words
A semiconductor memory device as claimed in claim 18, where said memory device is a read-only memory.
Claim 32
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 18 wherein all of said memory cells have substantially the same structures.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-19 | 1987-12-19 | 1988-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-19 | 1991-12-19 | 1992-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-19 | 1995-12-19 | 1996-06-19 | $7700.00 | Window Closed / Lapsed |