US4454503A
Expired / Lapsed
US
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Transistor fault indicator
Assignee: General Electric Co
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Filing: 1981-09-03
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Granted: 1984-06-12
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Expires: 2001-09-03
Abstract
Abstract A transistor fault indicator circuit monitors the conduction state of a transistor and compares that state to a commanded state. Differences in states are treated as faults and actuate an alarm or shut down the system including the transistor. In systems in which the transistor may be operated in a continuous conduction mode for long time periods, a control circuit is provided to periodically short circuit the base-emitter bias of the transistor to force a momentary period of nonconduction during which time the proper operation of the transistor can be verified.
Inventors
- 👤 Charles E. Konrad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:56
CPC Classifications
H; H02; H02H; H02H7/00; H02H7/08; H02H7/0833; H02H7/0844; G; G01; G01R; G01R31/00; G01R31/40
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
192 words
The fault indicator circuit for a first transistor having a base terminal, a collector terminal and an emitter terminal, the first transistor being connected in a series current path between a power source and a load, a source of control signals for selectively switching the first transistor between a conducting and a nonconducting state and means for coupling the control signals to the base terminal of the first transistor, the indicator circuit comprising: (a) switching means connected for selectively short circuiting the control signals applied to the base terminal of the first transistor whereby the first transistor is rendered nonconducting; (b) a source of gating pulses; (c) means for coupling said gating pulses to said switching means, said switching means being responsive to said gating pulses for short circuiting said control signals; (d) means connected for comparing the state of the gating pulses to a corresponding state of conduction of the first transistor, said comparing means providing an energizing signal upon detection of a difference between the gating pulse state and the state of conduction of the first transistor; and, (e) means responsive to said energizing signal for providing a fault indication.
Claim 2
Dependent Claim
192 words
The fault indicator circuit for a first transistor having a base terminal, a collector terminal and an emitter terminal, the first transistor being connected in a series current path between a power source and a load, a source of control signals for selectively switching the first transistor between a conducting and a nonconducting state and means for coupling the control signals to the base terminal of the first transistor, the indicator circuit comprising: (a) switching means connected for selectively short circuiting the control signals applied to the base terminal of the first transistor whereby the first transistor is rendered nonconducting; (b) a source of gating pulses; (c) means for coupling said gating pulses to said switching means, said switching means being responsive to said gating pulses for short circuiting said control signals; (d) means connected for comparing the state of the gating pulses to a corresponding state of conduction of the first transistor, said comparing means providing an energizing signal upon detection of a difference between the gating pulse state and the state of conduction of the first transistor; and, (e) means responsive to said energizing signal for providing a fault indication.
Claim 3
Dependent Claim
32 words
The fault indicator circuit of claim 1 wherein said switching means comprises a second transistor of an NPN type having a collector-emitter junction connected across a base-emitter junction of the first transistor.
Claim 4
Dependent Claim
43 words
The fault indicator circuit of Claim 1 wherein said comparing means comprises an exclusive OR circuit having a first input terminal connected to receive said gating pulses and a second input terminal connected to monitor the state of conduction of the first transistor.
Claim 5
Dependent Claim
202 words
The fault indicator circuit of claim 3 wherein the load comprises a plurality of electromechanical contactor coils and a multiposition switch for selectively connecting at least one of the coils in series circuit with the collector-emitter junction of the first transistor, the circuit further comprising: (a) an OR circuit having a plurality of input terminals, each input terminal being connected to a corresponding one of the contactor coils whereby said OR circuit provides an output signal when power is applied to any one of the coils; (b) a NAND logic circuit having a first input terminal connected to receive said output signal from said OR circuit and a second iput terminal connected to receive said energizing signal, whereby said energizing signal is inhibited until at least one of said coils has been connected to the power source; (c) a bistable flip-flop having a Q output terminal and having a set input terminal connected to an output terminal of said NAND circuit; (d) a lamp; (e) a silicon controlled rectifier arranged for connecting said lamp in a series circuit across the power source; and, (f) means for connecting the Q output terminal of said flip-flop to a gate terminal of said controlled rectifier.
Claim 6
Dependent Claim
47 words
The fault indicator circuit of claim 4 wherein said flip-flop includes a reset terminal, the circuit including a differentiation circuit for connecting the output terminal of said OR circuit to said reset terminal whereby said flip-flop is reset with each change in position of said multiposition switch.
Claim 7
Dependent Claim
126 words
A fault detection circuit for a normally conductive transistor regulating current to a load, comprising: first means providing a train of periodic pulses having a time duration between pulses which is relatively long with respect to the pulse time duration; second means receiving said pulses and responsive thereto to cause said transistor to switch to a non-conductive state during said pulse time duration; logic means simultaneously receiving said train of periodic pulses and a signal from said transistor which is indicative of the conductive state thereof, said logic means being responsive to said pulses and said signal to produce an output signal indicative of a fault in said transistor whenever said transistor remains in a conductive state simultaneously with the occurrence of said pulse time duration.
Claim 8
Dependent Claim
126 words
A fault detection circuit for a normally conductive transistor regulating current to a load, comprising: first means providing a train of periodic pulses having a time duration between pulses which is relatively long with respect to the pulse time duration; second means receiving said pulses and responsive thereto to cause said transistor to switch to a non-conductive state during said pulse time duration; logic means simultaneously receiving said train of periodic pulses and a signal from said transistor which is indicative of the conductive state thereof, said logic means being responsive to said pulses and said signal to produce an output signal indicative of a fault in said transistor whenever said transistor remains in a conductive state simultaneously with the occurrence of said pulse time duration.
Claim 9
Dependent Claim
44 words
The fault detection circuit of claim 6 wherein said second means comprises a switching means connected between the base and emitter terminals of said transistor, said switching means being responsive to said pulse duration to produce a short-circuit between said base and emitter terminals.
Claim 10
Dependent Claim
47 words
The fault detection circuit of claim 7 wherein said logic means comprises an exclusive OR circuit having a first input terminal connected to receive said train of periodic pulses and a second input terminal connected to receive the signal indicative of the conductive state of said transistor.
Claim 11
Dependent Claim
15 words
The fault detection circuit of claim 8 wherein said switching means comprises a second transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-12 | 1987-12-12 | 1988-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-12 | 1991-12-12 | 1992-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-12 | 1995-12-12 | 1996-06-12 | $7700.00 | Window Closed / Lapsed |