Fault detector circuit for electric vehicle control

Claim 2

Means for disabling an electrical drive system including an electric motor and power switching means for coupling the motor across a source of electrical energy, comprising: sensing means coupled to the power switching means for producing a fault signal in response to the persistence of conductivity of said power switching means beyond a predetermined period of time; disable means coupled to said sensing means and operable to interrupt the flow of power to the motor upon reception of a fault signal and to reapply power to the motor after the cessation of said fault signal and the reception of a reset signal; reset means coupled to said disable means for outputting a reset signal in response to each of a predetermined number of operations of said disable means; and means for transmitting reset signals from said reset means to said disable means.

Claim 3

The invention defined in claim 1, wherein said reset means produces a reset signal only in response to the initial operation of said disable means.

Claim 4

The invention defined in claim 2, wherein said reset means comprises: time delay means for outputting a reset signal during a predetermined time after the operation of said disable means; and first bistable means coupled to said time delay means for inhibiting said time delay means from producing subsequent reset signals.

Claim 5

The invention defined in claim 3, wherein said sensing means is coupled across said power switching means, said sensing means having an input impedance which is substantially higher than the impedance of an energized power switching means, but substantially lower than that of a deenergized power switching means.

Claim 6

The invention defined in claim 4, wherein said sensing means comprises a resistor-capacitor circuit whose time constant exceeds said predetermined period of time; said predetermined period of time being at least as long as a conductive interval of said power switching means.

Claim 7

The invention defined in claim 5, wherein said first bistable means is in a first state before the production of a first reset signal, and in a second state thereafter.

Claim 8

The invention defined in claim 6, wherein said disable means comprises a second bistable means.

Claim 9

The invention defined in claim 7, further including circuit means for coupling said first and said second bistable means to a source of power and for resetting said first and said second bistable means.

Claim 10

The invention defined in claim 8, wherein said circuit means comprises time delay means.

Claim 11

The invention defined in claim 9, further including variable impedance means coupled to said sensing means for varying said predetermined period of time.

Claim 12

A fault detector for disabling an electrical drive system including an electric motor and further including power switching means for repeatedly coupling the motor across a source of electrical energy, comprising: sensing means for producing a fault signal in response to a persistence in conducTivity of the power switching means beyond a first, predetermined period of time; means for coupling said sensing means to said power switching means; first bistable means coupled to said sensing means for producing a disable signal after the reception of said fault signal, and for maintaining said disable signal after termination of said fault signal until the reception thereby of a reset signal; circuit means coupled to said first bistable means for disabling the electrical drive system in response to the production of a disable signal; time delay means coupled to said first bistable means for outputting a reset signal a predetermined period of time after the production of a disable signal; second bistable means coupled to said time delay means for inhibiting said time delay means from producing subsequent reset signals; and means for coupling said reset signal to said first bistable means for causing said first bistable means to cease producing a disable signal in the absence of a fault signal.

Claim 13

A fault detector for disabling an electrical drive system including an electric motor and further including power switching means for repeatedly coupling the motor across a source of electrical energy, comprising: sensing means for producing a fault signal in response to a persistence in conducTivity of the power switching means beyond a first, predetermined period of time; means for coupling said sensing means to said power switching means; first bistable means coupled to said sensing means for producing a disable signal after the reception of said fault signal, and for maintaining said disable signal after termination of said fault signal until the reception thereby of a reset signal; circuit means coupled to said first bistable means for disabling the electrical drive system in response to the production of a disable signal; time delay means coupled to said first bistable means for outputting a reset signal a predetermined period of time after the production of a disable signal; second bistable means coupled to said time delay means for inhibiting said time delay means from producing subsequent reset signals; and means for coupling said reset signal to said first bistable means for causing said first bistable means to cease producing a disable signal in the absence of a fault signal.

Claim 14

The invention defined in claim 11, wherein said sensing means comprises a transistor, and said means coupling said sensing means to said power switching device comprises a circuit coupling said sensing means and said power switching device to a common source of electric potential.

Claim 15

The invention defined in claim 12, wherein said second bistable means is in a first state prior to the production by said time delay means of an initial reset signal, and further including second circuit means for applying said reset signal to said second bistable means to cause said second bistable means to assume a second state.

Claim 16

The invention defined in claim 13, further including a reset circuit for coupling said first and said second bistable means to a source of electric potential, said reset circuit comprising second time delay means.

Claim 17

The invention defined in claim 14, wherein said sensing means further comprises third time delay means.

Claim 18

The invention defined in claim 15, further including variable impedance means coupled to said third time delay means for varying said first, predetermined period of time.

Claim 19

The invention defined in claim 16, further including inhibit circuit means coupled to said sensing means for selectively preventing the operation thereof during the prolonged conduction of the power switching means.