Fabrication of MOS integrated circuit devices

Claim 1

A method of fabricating an MOS integrated circuit device that comprises metallic silicide-on-polysilicon-on-gate oxide-on-single-crystalline silicon portions, said method comprising in a single ion implantation step, doping regions in said single-crystalline silicon and, at the same time, doping said metallic silicide, and heating said device to define source and drain regions therein and, at the same time, to cause the dopants in said metallic silicide to diffuse to render the underlying polysilicon conductive.

Claim 2

A method of fabricating an MOS integrated circuit device that comprises metallic silicide-on-polysilicon-on-gate oxide-on-single-crystalline silicon portions, said method comprising in a single ion implantation step, doping regions in said single-crystalline silicon and, at the same time, doping said metallic silicide, and heating said device to define source and drain regions therein and, at the same time, to cause the dopants in said metallic silicide to diffuse to render the underlying polysilicon conductive.

Claim 3

A method of fabricating an MOS integrated circuit device that comprises metallic silicide-on-polysilicon-on-gate oxide-on-single-crystalline silicon portions and metallic silicide-on-polysilicon-on-single crystalline silicon portions, said method comprising in a single ion implantation step, doping source, drain and ohmic contact regions in said single-crystalline silicon and, at the same time, doping said metallic silicides, and heating said device to define source, drain and ohmic contact regions therein and, at the same time, to cause the dopants in said metallic silicides to diffuse to render the underlying polysilicon conductive and to render conductive the single-crystalline silicon underlying the polysilicon.

Claim 4

A method of fabricating an MOS integrated circuit device that comprises metallic silicide-on-polysilicon-on-gate oxide-on-single-crystalline silicon portions and metallic silicide-on-polysilicon-on-single crystalline silicon portions, said method comprising in a single ion implantation step, doping source, drain and ohmic contact regions in said single-crystalline silicon and, at the same time, doping said metallic silicides, and heating said device to define source, drain and ohmic contact regions therein and, at the same time, to cause the dopants in said metallic silicides to diffuse to render the underlying polysilicon conductive and to render conductive the single-crystalline silicon underlying the polysilicon.

Claim 9

A method of fabricating an MOS integrated circuit device of the type that includes MOS transistors each having spaced-apart source and drain portions formed in a single-crystalline silicon region, at least some of said transistors having associated therewith an ohmic contact portion formed in said region for establishing electrical contact with either of associated source and drain portions, each said transistor further having associated therewith a metallic silicide-on-polysilicon contact portion overlying said ohmic contact portion and each transistor comprising a metallic silicide-on-polysilicon-on-gate oxide portion overlying a portion in said single crystalline silicon region between said source and drain portions, said method comprising: in a single ion implantation step, doping said source and drain portions, said metallic silicide and said ohmic contact portion except for the portion directly underlying said metallic silicide-on-polysilicon contact portion, forming an insulating layer on the entire top surface of said device, and heating said insulating layer to cause the dopants introduced into said source, drain and ohmic contact portions to diffuse vertically and laterally to define the final extents of such portions in said device and to cause the dopants introduced into the metallic silicide to diffuse into the underlying polysilicon to render said polysilicon conductive and into the ohmic contact portion directly underlying said metallic silicide-on-polysilicon contact portion to render said portion conductive.

Claim 10

A method of fabricating an MOS integrated circuit device of the type that includes MOS transistors each having spaced-apart source and drain portions formed in a single-crystalline silicon region, at least some of said transistors having associated therewith an ohmic contact portion formed in said region for establishing electrical contact with either of associated source and drain portions, each said transistor further having associated therewith a metallic silicide-on-polysilicon contact portion overlying said ohmic contact portion and each transistor comprising a metallic silicide-on-polysilicon-on-gate oxide portion overlying a portion in said single crystalline silicon region between said source and drain portions, said method comprising: in a single ion implantation step, doping said source and drain portions, said metallic silicide and said ohmic contact portion except for the portion directly underlying said metallic silicide-on-polysilicon contact portion, forming an insulating layer on the entire top surface of said device, and heating said insulating layer to cause the dopants introduced into said source, drain and ohmic contact portions to diffuse vertically and laterally to define the final extents of such portions in said device and to cause the dopants introduced into the metallic silicide to diffuse into the underlying polysilicon to render said polysilicon conductive and into the ohmic contact portion directly underlying said metallic silicide-on-polysilicon contact portion to render said portion conductive.

Claim 15

A method of making an MOS integrated circuit device, comprising the steps of forming a structure comprising a metallic silicide-on-polysilicon pattern on a silicon body, said pattern comprising polysilicon portions in direct contact with the surface of said body and other polysilicon portions spaced apart from the surface of said body by a relatively thin insulating layer, implanting a dopant into the silicide portions of said pattern and into selected regions of said body that are uncovered or covered only with said relatively thin insulating layer, forming a relatively thick insulating layer on the entire top surface of said structure, and heating said structure to cause dopants in said silicide portions to diffuse into the polysilicon portions thereunder and into those portions of the body that have polysilicon directly thereover to render those polysilicon portions and body portions conductive and to cause the dopants in the selected regions of said body to diffuse therein to define source, drain and ohmic contact regions, said ohmic contact regions being electrically bridged by said conductive body portions and electrically contacting source or drain regions in said body.

Claim 16

A method of making an MOS integrated circuit device, comprising the steps of forming a structure comprising a metallic silicide-on-polysilicon pattern on a silicon body, said pattern comprising polysilicon portions in direct contact with the surface of said body and other polysilicon portions spaced apart from the surface of said body by a relatively thin insulating layer, implanting a dopant into the silicide portions of said pattern and into selected regions of said body that are uncovered or covered only with said relatively thin insulating layer, forming a relatively thick insulating layer on the entire top surface of said structure, and heating said structure to cause dopants in said silicide portions to diffuse into the polysilicon portions thereunder and into those portions of the body that have polysilicon directly thereover to render those polysilicon portions and body portions conductive and to cause the dopants in the selected regions of said body to diffuse therein to define source, drain and ohmic contact regions, said ohmic contact regions being electrically bridged by said conductive body portions and electrically contacting source or drain regions in said body.