Patent US4449066A successfully refreshed from Google Patents.
US4449066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer circuit for generating output signals having short recovery time
Assignee: Fujitsu Ltd
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Filing: 1981-12-16
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Granted: 1984-05-15
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Expires: 2001-12-16
Abstract
Abstract In a buffer circuit comprising a first, a second and a third transistor and a capacitor for bootstrap action, an inverter is connected to the output point at which the second and third transistors are connected in series, the inverter inverting the potential of the output point and supplying the inverted potential to the gate of the first transistor, thereby ensuring the quick rise of the leading edge of the output signal.
Inventors
- 👤 Keizo Aoyama
- 👤 Takahiko Yamauchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
202 words
A buffer circuit operatively connectable to a voltage source and operatively connected to receive an input signal, comprising: a capacitor; a first FET transistor having one of a source or drain which receives the input signal; a second FET transistor for performing a bootstrap function, having a source operatively connected to one terminal of said capacitor, having a gate operatively connected to the other of the drain or source of said first FET transistor, and the other terminal of said capacitor and having a drain operatively connected to the voltage source; a third FET transistor having a source or drain operatively connected in series with the source of said second FET transistor at an output point, and having a gate for receiving a signal which has an inverse phase of the phase of the input signal and which is slightly delayed from the input signal, and having the other of the source or drain connected to a reference voltage; and an inverter operatively connected to the output point at which said second and third FET transistors are connected in series, said inverter inverting the potential at the output point and supplying the inverted potential to the gate of said first FET transistor.
Claim 2
Dependent Claim
202 words
A buffer circuit operatively connectable to a voltage source and operatively connected to receive an input signal, comprising: a capacitor; a first FET transistor having one of a source or drain which receives the input signal; a second FET transistor for performing a bootstrap function, having a source operatively connected to one terminal of said capacitor, having a gate operatively connected to the other of the drain or source of said first FET transistor, and the other terminal of said capacitor and having a drain operatively connected to the voltage source; a third FET transistor having a source or drain operatively connected in series with the source of said second FET transistor at an output point, and having a gate for receiving a signal which has an inverse phase of the phase of the input signal and which is slightly delayed from the input signal, and having the other of the source or drain connected to a reference voltage; and an inverter operatively connected to the output point at which said second and third FET transistors are connected in series, said inverter inverting the potential at the output point and supplying the inverted potential to the gate of said first FET transistor.
Claim 3
Dependent Claim
35 words
A buffer circuit as defined in claim 1, wherein a fourth transistor is connected between the gate of said second FET transistor and the voltage source for precharging the gate of said second FET transistor.
Claim 4
Dependent Claim
47 words
A buffer circuit as defined in claim 1 or 2, wherein a fifth transistor is connected between said output point and the voltage source for supplying charges to said output point to prevent the potential of said output point from being reduced due to a junction leakage.
Claim 5
Dependent Claim
116 words
A buffer circuit comprising: a first transistor for receiving a first input signal; a second transistor for receiving an output from said first transistor; means connected with said second transistor for effecting a bootstrap function; a third transistor connected in series with said second transistor and providing an output signal point at the connection therebetween; means for providing a second input signal to said third transistor which is slightly delayed from and of inverse phase to said first input signal; and further means connected between the output signal point and the first transistor for providing an inverted output signal to said first transistor for effecting a quick rise of a leading edge of the output signal.
Claim 6
Dependent Claim
116 words
A buffer circuit comprising: a first transistor for receiving a first input signal; a second transistor for receiving an output from said first transistor; means connected with said second transistor for effecting a bootstrap function; a third transistor connected in series with said second transistor and providing an output signal point at the connection therebetween; means for providing a second input signal to said third transistor which is slightly delayed from and of inverse phase to said first input signal; and further means connected between the output signal point and the first transistor for providing an inverted output signal to said first transistor for effecting a quick rise of a leading edge of the output signal.
Claim 7
Dependent Claim
29 words
A buffer circuit as set forth in claim 4, wherein said further means includes an inverter connected between said output signal point and an input to said first transistor.
Claim 8
Dependent Claim
33 words
A buffer circuit as set forth in claim 5, wherein said means for providing a second input signal includes another inverter connected between the input to said first transistor and the third transistor.
Claim 9
Dependent Claim
22 words
A buffer circuit as set forth in claim 4, 5 or 6, wherein all said transistors are FETs of the enhancement type.
Claim 10
Dependent Claim
19 words
A buffer circuit as set forth in claim 5, wherein said inverter comprises two FET transistors connected in series.
Claim 11
Dependent Claim
31 words
A buffer circuit as set forth in claim 8, wherein a second inverter having FET transistors in series is connected between the input to said first transistor and the third transistor.
Claim 12
Dependent Claim
74 words
A buffer circuit as set forth in claim 7, wherein said first FET transistor has either the source or the drain receiving the input signal, said second FET transistor has its gate connected to the other of the drain or source of said first FET transistor, and said means connected with said second FET transistor to effect a bootstrap function comprises a capacitor connected between the gate and source of said second FET transistor.
Claim 13
Dependent Claim
36 words
A buffer circuit as set forth in claim 10, wherein a fourth transistor is connected between the gate of said second FET transistor and the voltage source for precharging the gate of said second FET transistor.
Claim 14
Dependent Claim
48 words
A buffer circuit as defined in claim 11, wherein a fifth transistor is connected between said output signal point and the voltage source for supplying charges to said output signal point to prevent the potential of said output signal point from being reduced due to transistor junction leakage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-15 | 1987-11-14 | 1988-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-15 | 1991-11-14 | 1992-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-15 | 1995-11-14 | 1996-05-15 | $7700.00 | Window Closed / Lapsed |