Semiconductor circuit with clock-controlled charge displacement devices

Claim 1

Semiconductor circuit comprising at least two clock-controlled charge-displacement devices respectively having a multiplicity of storage cells with respective information content, each of the storage cells of a first one of said charge-displacement devices being operatively associated with a respective storage cell of a second one of said charge-displacement devices, respective comparator circuits disposed between the respective associated storage cells of said first and second charge-displacement devices, each of said comparator circuits comprising two field-effect transistors and a diode mutually connected so as to afford a comparison of the information content in the respective associated storage cells, means for transferring the information content of the storage cells of one of said first and second charge-displacement devices to the respective storage cells of the other of said first and second charge-displacement devices operatively associated therewith so as to combine the transfered information content of the storage cells of said one charge-displacement device with the information content of the respective storage cells of said other charge-displacement device, and means operatively associated with one of said at least two clock-controlled charge-displacement devices for serially reading-out therethrough information obtained as a result of the information transfer.