Utilizing multi-layer mask to define isolation and device zones in a semiconductor substrate

Claim 1

A method of manufacturing a semiconductor integrated circuit having at least one semiconductor circuit element, which comprises: providing a semiconductor body comprising an epitaxial layer of a first conductivity type on a substrate of a second conductivity type opposite to that of the first; providing a third insulating layer directly on the semiconductor body surface; providing a first insulating layer of a material other than that of said third layer and comprising silicon nitride on said third insulating layer; providing a substantially planar and uniform second insulating layer of a material other than that of said first and said third layers on said first insulating layer; simultaneously providing apertures in said substantially planar and uniform second layer at a plurality of areas where surface-adjoining zones of said semiconductor circuit element are to be formed; including at least one aperture surrounding a semiconductor island in which said semiconductor circuit element is to be provided, to form a basic mask which will simultaneously and precisely define the dimensions and locations of all dimensionally-critical regions of the circuit element to be formed; then covering all but at least a part of said one surrounding aperture with a covering layer; then selectively removing said first insulating layer within the uncovered region; then selectively removing said third insulating layer within at least said part of said one aperture; then removing said covering layer; then selectively etching recesses in the uncovered semiconductor material in said one aperture; then thermally oxidizing the uncovered semiconductor material in said one aperture to selectively form a recessed oxide insulating zone extending down to said substrate and surrounding said island; then selectively removing the first insulating layer within all remaining apertures of the basic mask in the second insulating layer to form a replica of said remaining aperture in said first insulating layer without removing the underlying third insulating layer; and then selectively forming said surface-adjoining semiconductor zone of said semiconductor circuit element in at least one of said remaining apertures by ion implantation through said third insulating layer.

Claim 2

A method of manufacturing a semiconductor integrated circuit having at least one semiconductor circuit element, which comprises: providing a semiconductor body comprising an epitaxial layer of a first conductivity type on a substrate of a second conductivity type opposite to that of the first; providing a third insulating layer directly on the semiconductor body surface; providing a first insulating layer of a material other than that of said third layer and comprising silicon nitride on said third insulating layer; providing a substantially planar and uniform second insulating layer of a material other than that of said first and said third layers on said first insulating layer; simultaneously providing apertures in said substantially planar and uniform second layer at a plurality of areas where surface-adjoining zones of said semiconductor circuit element are to be formed; including at least one aperture surrounding a semiconductor island in which said semiconductor circuit element is to be provided, to form a basic mask which will simultaneously and precisely define the dimensions and locations of all dimensionally-critical regions of the circuit element to be formed; then covering all but at least a part of said one surrounding aperture with a covering layer; then selectively removing said first insulating layer within the uncovered region; then selectively removing said third insulating layer within at least said part of said one aperture; then removing said covering layer; then selectively etching recesses in the uncovered semiconductor material in said one aperture; then thermally oxidizing the uncovered semiconductor material in said one aperture to selectively form a recessed oxide insulating zone extending down to said substrate and surrounding said island; then selectively removing the first insulating layer within all remaining apertures of the basic mask in the second insulating layer to form a replica of said remaining aperture in said first insulating layer without removing the underlying third insulating layer; and then selectively forming said surface-adjoining semiconductor zone of said semiconductor circuit element in at least one of said remaining apertures by ion implantation through said third insulating layer.