Memory system for microprocessor with multiplexed address/data bus

Claim 2

A memory device comprising memory means having an M-bit address input and an 8-bit data output, where M is an integer greater than eight, the memory means accessing eight data bits to said output in response to an M-bit address on said input, the device having sixteen address/data terminals, means connecting said 8-bit data output to a selected eight of said terminals, means connecting said M-bit address input to M of said terminals which include said selected eight of said terminals, and gate means selectively connecting certain ones of said terminals to inputs of said M-bit address input.

Claim 3

A device according to claim 1 wherein the memory means includes an M-bit address latch at said input to receive the M-bit address, decoder means connected to outputs of the address latch to produce a decoded address output, and a memory array connected to receive said decoded address output and partitioned to include eight parallel data outputs, and wherein the device is a semiconductor integrated circuit.

Claim 4

A device according to claim 1 wherein said gate means is activated by a single input terminal to the device.

Claim 5

A device according to claim 3 wherein four of said selected eight of said terminals are not used for addresses when a given voltage is applied to said single input terminal.

Claim 6

A memory device comprising memeory means having an M-bit address input and an N-bit data output, where M and N are integers greater than two and M is greater than N, the memory means accessing an N-bit byte in response to an M-bit address on said input, the device having at least 2N address/data terminals, means connecting said N-bit data output to a selected subset of N of said terminals, means connecting said M-bit address input to M of said terminals which include said selected subset of N of said terminals.

Claim 7

A memory device comprising memeory means having an M-bit address input and an N-bit data output, where M and N are integers greater than two and M is greater than N, the memory means accessing an N-bit byte in response to an M-bit address on said input, the device having at least 2N address/data terminals, means connecting said N-bit data output to a selected subset of N of said terminals, means connecting said M-bit address input to M of said terminals which include said selected subset of N of said terminals.

Claim 8

A device according to claim 5 wherein the memory means includes an M-bit address latch at said input to receive said M-bit address, decoder means connected to outputs of the address latch to produce a decoded address output, and a memory array connected to receive said decoded address output and partitioned to include N parallel outputs, and wherein the device is a semiconductor integrated circuit.

Claim 9

A device according to claim 5 wherein the memory means is of the read/write type and includes an N-bit data input along with said N-bit data output, and the memory means includes means coupled to the data input and data output for selecting between data input and data output operations.

Claim 10

A digital processor system comprising a CPU, a multiplexed input/output bus, said CPU having a 2N-bit bidirectional data input/output port multiplexed with an M-bit address port and connected to said input/output bus, where M and N are integers greater than two and M is greater than N, a connector board having at least 2N-bit bidirectional multiplexed data/address bus connected to said input/output bus, a pair of memory devices each having 2N terminals and each having memory means with an M-bit address input and an N-bit data output, each of the memory means accessing N-bits of data in response to an M-bit address on said input, means within each memory device connecting said N-bit data output to a selected subset of N of said 2N terminals, means within each memory device connecting said M-bit address input to M of said 2N terminals including said selected subset, connecting means coupling a certain N lines of said data/address bus to said selected subset of said 2N terminals of one of said memory devices and coupling N lines of said bus different from said certain N lines to the selected subset of the other of said memory devices, M lines of said data/address bus being connected to M terminals on each of said memory devices.

Claim 11

A digital processor system comprising a CPU, a multiplexed input/output bus, said CPU having a 2N-bit bidirectional data input/output port multiplexed with an M-bit address port and connected to said input/output bus, where M and N are integers greater than two and M is greater than N, a connector board having at least 2N-bit bidirectional multiplexed data/address bus connected to said input/output bus, a pair of memory devices each having 2N terminals and each having memory means with an M-bit address input and an N-bit data output, each of the memory means accessing N-bits of data in response to an M-bit address on said input, means within each memory device connecting said N-bit data output to a selected subset of N of said 2N terminals, means within each memory device connecting said M-bit address input to M of said 2N terminals including said selected subset, connecting means coupling a certain N lines of said data/address bus to said selected subset of said 2N terminals of one of said memory devices and coupling N lines of said bus different from said certain N lines to the selected subset of the other of said memory devices, M lines of said data/address bus being connected to M terminals on each of said memory devices.

Claim 12

A system according to claim 8 including conductor means within said other of the memory devices connecting some of said terminals to part of said M-bit address input of the memory means.

Claim 13

A system according to claim 9 wherein both of said memory device include said conductor means but such conductor means is inactivated in said one of the memory devices.

Claim 14

A system according to claim 10 wherein N is eight and M is twelve.

Claim 15

A system according to claim 11 wherein said conductor means includes parallel gate means activated by a given voltage on a byte select terminal on each of the memory devices.

Claim 16

A memory system for use in a digital processor system which has 2N multiplexed bidirectional access lines comprising a first and a second memory, each said memory having a plurality of terminals connected to said access lines, said terminals of each memory including an M-bit address input and an N-bit data output, where M and N are integers and M is greater than N, each said memory accessing an N-bit byte in response to an M-bit address on said input, said terminals of each said memory being the same pattern of 2N multiplexed address/data means in each said first and second memory connecting said N-bit data output to a selected subset of N of said terminals, such selected subset in the first memory being different from such selected subset of the second memory, means in each said memory connecting said M-bit address input to M of said terminals which include said selected subset of N of said terminals for such memory.

Claim 17

A memory system for use in a digital processor system which has 2N multiplexed bidirectional access lines comprising a first and a second memory, each said memory having a plurality of terminals connected to said access lines, said terminals of each memory including an M-bit address input and an N-bit data output, where M and N are integers and M is greater than N, each said memory accessing an N-bit byte in response to an M-bit address on said input, said terminals of each said memory being the same pattern of 2N multiplexed address/data means in each said first and second memory connecting said N-bit data output to a selected subset of N of said terminals, such selected subset in the first memory being different from such selected subset of the second memory, means in each said memory connecting said M-bit address input to M of said terminals which include said selected subset of N of said terminals for such memory.

Claim 18

A system according to claim 13 where said selected subset of N of said terminals of the first memory is connected to one set of N of said access lines and said selected subset of N of said terminals of the second memory is connected to a different set of N of said access lines.

Claim 19

A digital processor system comprising: a bidirectional multiplexed address/data bus; a CPU having a 2N-bit bidirectional data input/output port multiplexed with an M-bit address port at CPU terminals, where M and N are integers greater than two and M is greater than N, said CPU terminals being connected to said bus, a connector board having at least 2N-bit bidirectional multiplexed data/address lines connected to said bus, a pair of memory devices each having 2N terminals, each of the pair of memory devices having memory means with an M-bit address input and an N-bit data output, each of the memory means accessing N-bits of data in response to an M-bit address on said input, means within each memory device connecting said N-bit data output to a selected subset of N of said 2N terminals, means within each memory device connecting said M-bit address input to a different set of M of said 2N terminals including said subset, connecting means coupling N lines of said bus to said selected subset of said 2N terminals of one of said memory devices and a different N lines of said bus to the selected subset of the other of said memory devices, M lines of said bus being coupled to M of said terminals on each of said memory devices.

Claim 20

A digital processor system comprising: a bidirectional multiplexed address/data bus; a CPU having a 2N-bit bidirectional data input/output port multiplexed with an M-bit address port at CPU terminals, where M and N are integers greater than two and M is greater than N, said CPU terminals being connected to said bus, a connector board having at least 2N-bit bidirectional multiplexed data/address lines connected to said bus, a pair of memory devices each having 2N terminals, each of the pair of memory devices having memory means with an M-bit address input and an N-bit data output, each of the memory means accessing N-bits of data in response to an M-bit address on said input, means within each memory device connecting said N-bit data output to a selected subset of N of said 2N terminals, means within each memory device connecting said M-bit address input to a different set of M of said 2N terminals including said subset, connecting means coupling N lines of said bus to said selected subset of said 2N terminals of one of said memory devices and a different N lines of said bus to the selected subset of the other of said memory devices, M lines of said bus being coupled to M of said terminals on each of said memory devices.

Claim 21

A system according to claim 15 wherein N is eight and M is at least twelve.