Abstract A variable organization memory system of two memory segments, each segment being of 1024 memory word by 9 data bit capacity. The segments are preferably semiconductor memory cells. Complete addressing capability for the maximum (2,048) memory word depth required is provided, while complete data line capability for the maximum (18) data bit length is included. System organization is varied by proper interconnection of various modifying input lines for memory word dimension and by driving data in and data out lines in parallel for the data bit dimension. Thus, for a 1024 memory word by 18 data bit organization, output levels to the memory segments from a buffer invert modifying input are permanently at an up logic level. This enables the two memory segments and gates set pulses to the data lines of both segments. Alternatively, when a 2,048 memory word by 9 data bit organization is desired, the inverted output from a buffered modifying input to the first memory segment is reinverted to the true complement of the input on the first modifying input and connected to the second memory segment while the data lines are driven in parallel.
A variable organization memory system comprising a memory system including a first and second memory segment, each segment comprising a plurality of memory storage locations providing a m/2 word by n/2 bit memory organization array; means within said memory system for selecting the m/2 word by n/2 bit memory organization array of each segment to provide a memory system having either a m word by n/2 bit memory organization array or a m/2 word by n bit memory organization array while maintaining constant the total number of storage locations of said memory system wherein m is the maximum number of words and n is the maximum number of bits; and address and data lines connected to said system, the number of address lines being sufficient for accessing said m words and the number of data lines being sufficient for accessing said n bits.
Claim 2
Dependent Claim
143 words
A variable organization memory system comprising a memory system including a first and second memory segment, each segment comprising a plurality of memory storage locations providing a m/2 word by n/2 bit memory organization array; means within said memory system for selecting the m/2 word by n/2 bit memory organization array of each segment to provide a memory system having either a m word by n/2 bit memory organization array or a m/2 word by n bit memory organization array while maintaining constant the total number of storage locations of said memory system wherein m is the maximum number of words and n is the maximum number of bits; and address and data lines connected to said system, the number of address lines being sufficient for accessing said m words and the number of data lines being sufficient for accessing said n bits.
Claim 3
Dependent Claim
18 words
A variable organization memory system in accordance with claim 1 wherein said memory system is a semiconductor system.
Claim 4
Dependent Claim
55 words
A variable organization memory system in accordance with claim 2 wherein said selecting means comprises true and complement means responsive to at least one of said address lines for enabling both of said segments to provide said m/2 word by n bit memory organization array or said m word by n/2 bit memory organization array.