Patent US4440580A successfully refreshed from Google Patents.
US4440580A
Expired / Lapsed
US
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Method of fabricating an integrated bipolar planar transistor by implanting base and emitter regions through the same insulating layer
Assignee: ITT Inc
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Filing: 1982-03-31
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Granted: 1984-04-03
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Expires: 2002-03-31
Abstract
Abstract The invention relates to an ion-implantation process for fabricating integrated bipolar planar transistors, particularly transistors for very high frequencies. To prevent the variations in the thicknesss of the insulating layer, through which the dopants for the base region are implanted into the semiconductor body in the form of ions, from causing variations in current gain, the dopants for the emitter regions are implanted through the same insulating layer as the dopants for the base region. The total charge in the base region below the emitter region thus becomes substantially independent of thickness variations of the insulating layer through which the dopants for the emitter region and those for the base region are implanted.
Inventors
- 👤 Hans-Juergen Gahle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:33
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
220 words
A method of fabricating an integrated bipolar planar transistor whose base region is formed by ion implantation through an insulating layer of a given thickness and composition of a first insulating material deposited on a semiconductor body, and whose emitter region is also formed by ion implantation, wherein the improvement comprises the steps of ion implanting the dopants of a first conductivity type for the emitter region through the same insulating layer as those for the base region forming a first photoresist mask layer having a selected opening; over the insulating layer, implanting ions of a second conductivity type into a portion of the surface of the semiconductor body below said opening, which portion is doped so as to be of the first conductivity type; removing the first photoresist mask layer; depositing an additional insulating layer made of a second material which is etchable selectively with respect to the first material; opening at least one window in the additional insulating layer at least where the emitter region is to be formed; covering the remaining portions of the additional insulating layer with a second photoresist mask layer; implanting ions of the first conductivity type into the semiconductor surface through the exposed portions of the insulating layer; removing the second photoresist mask layer; and activating the implanted ions during a post-diffusion process.
Claim 2
Independent Claim
220 words
A method of fabricating an integrated bipolar planar transistor whose base region is formed by ion implantation through an insulating layer of a given thickness and composition of a first insulating material deposited on a semiconductor body, and whose emitter region is also formed by ion implantation, wherein the improvement comprises the steps of ion implanting the dopants of a first conductivity type for the emitter region through the same insulating layer as those for the base region forming a first photoresist mask layer having a selected opening; over the insulating layer, implanting ions of a second conductivity type into a portion of the surface of the semiconductor body below said opening, which portion is doped so as to be of the first conductivity type; removing the first photoresist mask layer; depositing an additional insulating layer made of a second material which is etchable selectively with respect to the first material; opening at least one window in the additional insulating layer at least where the emitter region is to be formed; covering the remaining portions of the additional insulating layer with a second photoresist mask layer; implanting ions of the first conductivity type into the semiconductor surface through the exposed portions of the insulating layer; removing the second photoresist mask layer; and activating the implanted ions during a post-diffusion process.
Claim 3
Dependent Claim
122 words
A method as claimed in claim 1, wherein boron ions are implanted through the opening in the first photoresist mask layer to form a base region in an n-type surface area of a Si semiconductor body; after deposition of the additional insulating layer, the latter is provided with a first window where the emitter region is to be formed, a second window where a base contact region is to be formed, and a third window where a collector contact region is to be formed; the remaining portions of the additional insulating layer and the second window are covered with the second photoresist mask layer; and arsenic ions are then implanted into the semiconductor surface through the exposed areas of the insulating layer.
Claim 4
Dependent Claim
29 words
A method as claimed in claim 2, wherein the insulating layer is formed of SiO 2 and the additional insulating layer is formed of Si 3 N 4 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-03 | 1987-10-03 | 1988-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-03 | 1991-10-03 | 1992-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-03 | 1995-10-03 | 1996-04-03 | $7700.00 | Window Closed / Lapsed |