Method for making semiconductor device having improved thermal stress characteristics

Claim 1

A method of manufacturing a semiconductor device comprising the steps of providing a semiconductor layer with a main surface, forming a first semiconductor region making a PN junction with said semiconductor layer, said PN junction reaching said main surface, forming an insulating layer having a hole for exposing at least a part of said first semiconductor region on said main surface, introducing impurities having the same conductivity type as said first semiconductor region in said semiconductor layer through said hole of said insulating layer to form a second semiconductor region having a depth which is shallower than the depth of said first semiconductor region, said second semiconductor region making contact with said first semiconductor region, and forming a metal-semiconductor alloy layer electrically connected to said second semiconductor region.

Claim 2

A method of manufacturing a semiconductor device comprising the steps of providing a semiconductor layer with a main surface, forming a first semiconductor region making a PN junction with said semiconductor layer, said PN junction reaching said main surface, forming an insulating layer having a hole for exposing at least a part of said first semiconductor region on said main surface, introducing impurities having the same conductivity type as said first semiconductor region in said semiconductor layer through said hole of said insulating layer to form a second semiconductor region having a depth which is shallower than the depth of said first semiconductor region, said second semiconductor region making contact with said first semiconductor region, and forming a metal-semiconductor alloy layer electrically connected to said second semiconductor region.

Claim 3

A method of manufacturing a semiconductor device comprising the steps of introducing first impurities representing one conductivity type into a semiconductor layer of the opposite conductivity type to form a first semiconductor region making a P-N junction with said semiconductor layer, covering the surface of said first semiconductor region with an insulating layer having a hole for exposing a portion of the surface of said first semiconductor region, depositing a poly-crystalline semiconductor layer in said hole of said insulating layer, introducing second impurities representing said one conductivity type and having a diffusion coefficient larger than the diffusion coefficient of said first impurities, said second impurities being introduced into said exposed portion through said poly-crystalline semiconductor layer to form a second semiconductor region of one conductivity type making contact with said first semiconductor region, depositing a non-doped semiconductor layer on said poly-crystalline semiconductor layer, depositing a metal layer on said non-doped semiconductor layer, and performing a heat treatment to produce a metal-semiconductor alloy layer of said non-doped semiconductor layer and said metal layer.

Claim 4

A method of manufacturing a semiconductor device comprising the steps of introducing first impurities representing one conductivity type into a semiconductor layer of the opposite conductivity type to form a first semiconductor region making a P-N junction with said semiconductor layer, covering the surface of said first semiconductor region with an insulating layer having a hole for exposing a portion of the surface of said first semiconductor region, depositing a poly-crystalline semiconductor layer in said hole of said insulating layer, introducing second impurities representing said one conductivity type and having a diffusion coefficient larger than the diffusion coefficient of said first impurities, said second impurities being introduced into said exposed portion through said poly-crystalline semiconductor layer to form a second semiconductor region of one conductivity type making contact with said first semiconductor region, depositing a non-doped semiconductor layer on said poly-crystalline semiconductor layer, depositing a metal layer on said non-doped semiconductor layer, and performing a heat treatment to produce a metal-semiconductor alloy layer of said non-doped semiconductor layer and said metal layer.

Claim 6

A method of producing a field effect transistor comprising the steps of forming source and drain regions of one conductivity type in a semiconductor layer of the opposite conductivity type, forming a gate on said semiconductor layer through a gate insulating film for controlling an electrical path between said source and drain regions, covering the surface of said semiconductor layer with an insulative layer having a first hole exposing a portion of at least one of said source rgion and said drain region, introducing impurities representing said one conductivity type in said semiconductor layer through said first hole of said insulative layer to form a first semiconductor region of said one conductivity type having a depth which is shallower than the depth of said source and drain regions, said first semiconductor region making contact with said one of said source and drain regions, and forming a metal-semiconductor alloy layer on said first semiconductor region.

Claim 7

A method of producing a field effect transistor comprising the steps of forming source and drain regions of one conductivity type in a semiconductor layer of the opposite conductivity type, forming a gate on said semiconductor layer through a gate insulating film for controlling an electrical path between said source and drain regions, covering the surface of said semiconductor layer with an insulative layer having a first hole exposing a portion of at least one of said source rgion and said drain region, introducing impurities representing said one conductivity type in said semiconductor layer through said first hole of said insulative layer to form a first semiconductor region of said one conductivity type having a depth which is shallower than the depth of said source and drain regions, said first semiconductor region making contact with said one of said source and drain regions, and forming a metal-semiconductor alloy layer on said first semiconductor region.

Claim 8

A method of manufacturing a complementary semiconductor device comprising the steps of forming a well region of a first conductivity type in a semiconductor substrate of a second conductivity type, forming a first gate on said well region and a second gate on said semiconductor substrate through a gate insulating film, respectively, introducing first impurities of said second conductivity type into said well region to form first drain and first source regions of said second conductivity type which cooperate with said first gate to constitute a first transistor of a first channel type, introducing second impurities of said first conductivity type into said semiconductor substrate to form second drain and second source regions of said first conductivity type which cooperate with said second gate to constitute a second transistor of a second channel type, forming an insulative layer over surfaces of said well region and said semiconductor substrate, forming first and second contact holes for at least one of said first drain and first source regions and for at least one of said second drain and second source regions, respectively, forming a poly-crystalline semiconductor layer in said first contact hole, introducing third impurities of said second conductivity type having a diffusion coefficient larger than the diffusion coefficient of said first impurities, said third impurities being introduced through said poly-crystalline semiconductor layer into said one of said first drain and source regions to form a first semiconductor region of said second conductivity type, introducing said second impurities into said semiconductor substrate through said second contact hole to form a second semiconductor region having a depth which is shallower than the depth of said second drain and second source regions and making contact with said one of said second drain and second source regions, and forming metal-semiconductor alloy layers on said poly-crystalline semiconductor layer and in said second contact hole of said insulative layer to serve as electrodes for said at least one of said first drain and first source regions and for said at least one of said second drain and second source regions, respectively.

Claim 9

A method of manufacturing a complementary semiconductor device comprising the steps of forming a well region of a first conductivity type in a semiconductor substrate of a second conductivity type, forming a first gate on said well region and a second gate on said semiconductor substrate through a gate insulating film, respectively, introducing first impurities of said second conductivity type into said well region to form first drain and first source regions of said second conductivity type which cooperate with said first gate to constitute a first transistor of a first channel type, introducing second impurities of said first conductivity type into said semiconductor substrate to form second drain and second source regions of said first conductivity type which cooperate with said second gate to constitute a second transistor of a second channel type, forming an insulative layer over surfaces of said well region and said semiconductor substrate, forming first and second contact holes for at least one of said first drain and first source regions and for at least one of said second drain and second source regions, respectively, forming a poly-crystalline semiconductor layer in said first contact hole, introducing third impurities of said second conductivity type having a diffusion coefficient larger than the diffusion coefficient of said first impurities, said third impurities being introduced through said poly-crystalline semiconductor layer into said one of said first drain and source regions to form a first semiconductor region of said second conductivity type, introducing said second impurities into said semiconductor substrate through said second contact hole to form a second semiconductor region having a depth which is shallower than the depth of said second drain and second source regions and making contact with said one of said second drain and second source regions, and forming metal-semiconductor alloy layers on said poly-crystalline semiconductor layer and in said second contact hole of said insulative layer to serve as electrodes for said at least one of said first drain and first source regions and for said at least one of said second drain and second source regions, respectively.

Claim 12

A method of manufacturing a complementary semiconductor device comprising the steps of providing a semiconductor substrate of one conductivity type having a first zone in which a first transistor of a first channel type is formed and a second zone in which a second transistor of a second channel type is formed; forming a well region of the opposite conductivity type in said first zone of said semiconductor substrate; forming a first insulated gate of said first transistor on said well region and a second insulated gate of said second transistor on said second zone of said semiconductor substrate; introducing first impurities representing said one conductivity type into said well region by making use of said first insulated gate as a mask to form first drain and source regions of said first transistor; introducing second impurities representing said opposite conductivity type into said second zone of sais semiconductor substrate by making use of said second insulated gate as a mask to form second drain and source regions of said second transistor; covering said well region, said second zone of said semiconductor substrate, and said first and second insulated gates with an insulating layer having first, second, third and fourth contact holes provided for said first drain, first source, second drain, and second source regions, respectively; forming first and second poly-crystalline semiconductor layers covering said first and second contact holes of said insulating layer; masking said third and fourth contact holes of said insulating layer to introduce third impurities representing said one conductivity type and having a diffusion coefficient which is larger than the diffusion coefficient of said first impurities; introducing said third impurities into said well region through said first and second poly-crystalline semiconductor layers, said third impurities forming first and second semiconductor regions which are electrically connected to said first drain, and source rgions, respectively; said first and second poly-crystalline semiconductor layers being doped with said third impurities to serve as an interconnection layer; masking said first and second poly-crystalline layers to introduce fourth impurities which are the same as said second impurities into said second zone of said semiconductor substrate; introducing said fourth impurities through said third and fourth contact holes of said insulating layer, said fourth impurities forming third and fourth semiconductor regions which are electrically connected to said second drain and source regions, respectively, said third and fourth semiconductor regions having a depth which is shallower than the depth of said second source and drain regions; depositing a non-doped semiconductor layer covering said insulating film, said first and second poly-crystalline semiconductor layers, and said third and fourth contact holes; depositing a metal layer on said non-doped semiconductor layer; patterning said metal layer by reactive dry etching; patterning said non-doped semiconductor layer by making use of the patterned metal layer as a mask; and alloying the patterned metal layer with the patterned non-doped semiconductor layer to form metal-semiconductor alloy layers connecting to said first and second poly-crystalline semiconductor layers and covering said third and fourth contact holes, respectively, the thickness of said non-doped semiconductor layer being selected so that an etchant of said reactive dry etching does not damage said semiconductor substrate.

Claim 13

A method of manufacturing a complementary semiconductor device comprising the steps of providing a semiconductor substrate of one conductivity type having a first zone in which a first transistor of a first channel type is formed and a second zone in which a second transistor of a second channel type is formed; forming a well region of the opposite conductivity type in said first zone of said semiconductor substrate; forming a first insulated gate of said first transistor on said well region and a second insulated gate of said second transistor on said second zone of said semiconductor substrate; introducing first impurities representing said one conductivity type into said well region by making use of said first insulated gate as a mask to form first drain and source regions of said first transistor; introducing second impurities representing said opposite conductivity type into said second zone of sais semiconductor substrate by making use of said second insulated gate as a mask to form second drain and source regions of said second transistor; covering said well region, said second zone of said semiconductor substrate, and said first and second insulated gates with an insulating layer having first, second, third and fourth contact holes provided for said first drain, first source, second drain, and second source regions, respectively; forming first and second poly-crystalline semiconductor layers covering said first and second contact holes of said insulating layer; masking said third and fourth contact holes of said insulating layer to introduce third impurities representing said one conductivity type and having a diffusion coefficient which is larger than the diffusion coefficient of said first impurities; introducing said third impurities into said well region through said first and second poly-crystalline semiconductor layers, said third impurities forming first and second semiconductor regions which are electrically connected to said first drain, and source rgions, respectively; said first and second poly-crystalline semiconductor layers being doped with said third impurities to serve as an interconnection layer; masking said first and second poly-crystalline layers to introduce fourth impurities which are the same as said second impurities into said second zone of said semiconductor substrate; introducing said fourth impurities through said third and fourth contact holes of said insulating layer, said fourth impurities forming third and fourth semiconductor regions which are electrically connected to said second drain and source regions, respectively, said third and fourth semiconductor regions having a depth which is shallower than the depth of said second source and drain regions; depositing a non-doped semiconductor layer covering said insulating film, said first and second poly-crystalline semiconductor layers, and said third and fourth contact holes; depositing a metal layer on said non-doped semiconductor layer; patterning said metal layer by reactive dry etching; patterning said non-doped semiconductor layer by making use of the patterned metal layer as a mask; and alloying the patterned metal layer with the patterned non-doped semiconductor layer to form metal-semiconductor alloy layers connecting to said first and second poly-crystalline semiconductor layers and covering said third and fourth contact holes, respectively, the thickness of said non-doped semiconductor layer being selected so that an etchant of said reactive dry etching does not damage said semiconductor substrate.