Longitudinal parity

Claim 2

In a data processing system having a plurality of memory modules, each memory module having a plurality of memory locations for storing data bits, said data processing system having a parity memory location for storing parity bits, the improvement comprising: a correction word memory location in each of said memory modules for storing correction word bits in each of said modules, the parity bits stored in said parity memory location being computed by logically combining said correction word bits with the data bits stored in said memory modules, so that a change in the data bits stored in one of said memory modules can be accompanied by a change in the correction word bits stored in that one memory module so as not to require a change in the parity bits stored in said parity memory location.

Claim 3

A data processing memory system with a longitudinal parity arrangement, comprising: a plurality of memory modules, each memory module having a plurality of addressable memory locations for storing a data word or the like, at each of said addressable memory locations each data word being comprised of bits; a longitudinal parity word stored in a memory location in one of said modules; and a correction word stored in a memory location in each memory module other than the one memory module storing said longitudinal parity word, said parity word being computed by logically combining bits of the data words and the correction words stored in said memory modules, and said correction word being changeable each time a data word in its memory module is changed so that the value of said longitudinal parity word can remain at a constant value representing the logical combination of the data words and the correction words even when one of the data words is changed.

Claim 4

A data processing memory system with a longitudinal parity arrangement, comprising: a plurality of memory modules, each memory module having a plurality of addressable memory locations for storing a data word or the like, at each of said addressable memory locations each data word being comprised of bits; a longitudinal parity word stored in a memory location in one of said modules; and a correction word stored in a memory location in each memory module other than the one memory module storing said longitudinal parity word, said parity word being computed by logically combining bits of the data words and the correction words stored in said memory modules, and said correction word being changeable each time a data word in its memory module is changed so that the value of said longitudinal parity word can remain at a constant value representing the logical combination of the data words and the correction words even when one of the data words is changed.

Claim 5

The system of claim 2, wherein each of said memory modules is a read-only memory.

Claim 6

The system of claim 2, further comprising a microprocessor, and wherein the data words stored in said memory modules provide control routines for controlling the operation of said microprocessor.

Claim 7

The system of claim 4, wherein said microprocessor is a peripheral control processor, wherein said peripheral control processor comprises an input/output random access memory for receiving macrocommands from a central system for specifying the operation of a peripheral device, and wherein said microprocessor is controlled by said memory modules in order to store primitive commands in said input/output random access memory for controlling said peripheral device to operate in accordance with the macrocommands.

Claim 8

The system of claim 4, wherein said microprocessor is operated in accordance with a diagnostic routine that causes the data words in said memory modules to be read, a check sum to be computed from the read data, and a comparison made of the check sum with said longitudinal parity word.

Claim 9

The system of claim 2, wherein said correction word is comprised of a plurality of bits, with each bit having an initial value of binary zero, and wherein bits of said correction word are changed to a new value each time a data word is changed, by logically combining the value of the data word before the change, the value of the data word after the change, and the prior value of the correction word.

Claim 10

The system of claim 7, wherein the new value of the correction word is obtained by EXCLUSIVE ORing corresponding bits of the data word before the change, the data word after the change, and the prior correction word.