Patent US4423547A successfully refreshed from Google Patents.
US4423547A
Expired / Lapsed
US
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Method for forming dense multilevel interconnection metallurgy for semiconductor devices
Assignee: International Business Machines Corp
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Filing: 1981-06-01
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Granted: 1984-01-03
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Expires: 2001-06-01
Abstract
Abstract A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.
Inventors
- 👤 Paul A. Farrar
- 👤 Robert M. Geffken
- 👤 Charles T. Kroll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:19
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; H10P; H10P76/00; H10P76/20; H10P76/202
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
The method for providing multilevel interconnections for an integrated circuit comprising the steps of: providing a first patterned layer of interconnect metallurgy on the surface of a semiconductor substrate passivated with an oxide of silicon; blanket depositing a layer of silicon nitride over said substrate; photolithographically defining overlap via holes only through said silicon nitride layer to expose portions of said first patterned layer where interlevel contacts are desired; blanket depositing a layer of organic dielectric material over said substrates said organic dielectric layer being thicker than said silicon nitride layer; photolithographically defining oversized via holes, larger than said overlap via holes, in said organic dielectric layer to expose said overlap via holes and to re-expose said portions of said first patterned layer; and depositing a second patterned layer of interconnection metallurgy over said substrate to form continuous interconnection segments contacting said first patterned layer through said overlap and oversized via holes and passing over at least portions of said organic dielectric layer and said silicon nitride layer.
Claim 2
Independent Claim
168 words
The method for providing multilevel interconnections for an integrated circuit comprising the steps of: providing a first patterned layer of interconnect metallurgy on the surface of a semiconductor substrate passivated with an oxide of silicon; blanket depositing a layer of silicon nitride over said substrate; photolithographically defining overlap via holes only through said silicon nitride layer to expose portions of said first patterned layer where interlevel contacts are desired; blanket depositing a layer of organic dielectric material over said substrates said organic dielectric layer being thicker than said silicon nitride layer; photolithographically defining oversized via holes, larger than said overlap via holes, in said organic dielectric layer to expose said overlap via holes and to re-expose said portions of said first patterned layer; and depositing a second patterned layer of interconnection metallurgy over said substrate to form continuous interconnection segments contacting said first patterned layer through said overlap and oversized via holes and passing over at least portions of said organic dielectric layer and said silicon nitride layer.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said first and second patterned layers comprise aluminum.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said organic dielectric material is capable of forming a polyimide upon curing.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein said via holes are defined by plasma etching.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said patterned layers are deposited by a lift-off technique.
Claim 7
Dependent Claim
25 words
The method of claim 1 wherein the ratio of the thickness of said nitride layer and said organic dielectric material is about one to two.
Claim 8
Dependent Claim
16 words
The method of claim 6 wherein said silicon nitride layer is about 7000 Angstroms in thickness.
Claim 9
Dependent Claim
34 words
The method of claim 1 wherein said first patterned layer of interconnection metallurgy is selectively in contact with a polysilicon layer and said oxide of silicon is at least partially formed of oxidized polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-02 | 1987-07-04 | 1988-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-02 | 1991-07-04 | 1992-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-02 | 1995-07-04 | 1996-01-03 | $7700.00 | Window Closed / Lapsed |