Forming a compact multilevel interconnection metallurgy system for semi-conductor devices

Claim 1

A METHOD OF FABRICATING A MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR AN INTEGRATED SEMICONDUCTOR DEVICE COMPRISING FORMING A FIRST DIELECTRIC LAYER ON THE SURFACE OF A SEMICONDUCTOR SUBSTRATE, FORMING A FIRST LAYER OF FIRST METAL ON SAID FIRST DIELECTRIC LAYER, FORMING A FIRST METALLURGY INTERCONNECTION PATTERN HAVING UNIFORM WIDTH STRIPES IN THE FIRST LAYER OF METAL BY SELECTIVE REMOVAL OF PORTIONS THEREOF, DEPOSITION A SECOND DIELECTRIC LAYER OVER THE FIRST METALLURY LAYER OF SAID FIRST DIELECTRIC LAYER, SAID SECOND DIELECTRIC LAYER OF A MATERIAL DISSIMILAR FROM SAID FIRST DIELECTRIC LAYER, FORMING VIA HOLES IN SAID SECOND DIELECTRIC LAYER OF A DIAMETER SUBSTANTIIALLY EQUAL TO OR LARGER THAN THE WIDTH OF THE UNDERLYING CONDUCTIVE LINES OF THE FIRST METALLURGY PATTERN USING AN ETCHANT THAT IS SELECTIVE TO THE MATERIAL OF THE SECOND DIELECTRIC LAYER, FORMING A SECOND METALLURRY LAYER OF A SECOND METAL HAVING DISSIMILAR ETCHING CHARACTERISTICS THAN SAID FIRST METAL OVER THE SECOND DIELECTRIIC LAYER, AND FORMING AN INTERCONNECTION PATTERN IN THE SECOND METALLURGY LAYER WITH UNIFORM WIDTH LINES OVER THE VIA HOLES USING AN ETCHANT SELECTIVE TO SAID SECOND METAL.

Claim 2

A METHOD OF FABRICATING A MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEM FOR AN INTEGRATED SEMICONDUCTOR DEVICE COMPRISING FORMING A FIRST DIELECTRIC LAYER ON THE SURFACE OF A SEMICONDUCTOR SUBSTRATE, FORMING A FIRST LAYER OF FIRST METAL ON SAID FIRST DIELECTRIC LAYER, FORMING A FIRST METALLURGY INTERCONNECTION PATTERN HAVING UNIFORM WIDTH STRIPES IN THE FIRST LAYER OF METAL BY SELECTIVE REMOVAL OF PORTIONS THEREOF, DEPOSITION A SECOND DIELECTRIC LAYER OVER THE FIRST METALLURY LAYER OF SAID FIRST DIELECTRIC LAYER, SAID SECOND DIELECTRIC LAYER OF A MATERIAL DISSIMILAR FROM SAID FIRST DIELECTRIC LAYER, FORMING VIA HOLES IN SAID SECOND DIELECTRIC LAYER OF A DIAMETER SUBSTANTIIALLY EQUAL TO OR LARGER THAN THE WIDTH OF THE UNDERLYING CONDUCTIVE LINES OF THE FIRST METALLURGY PATTERN USING AN ETCHANT THAT IS SELECTIVE TO THE MATERIAL OF THE SECOND DIELECTRIC LAYER, FORMING A SECOND METALLURRY LAYER OF A SECOND METAL HAVING DISSIMILAR ETCHING CHARACTERISTICS THAN SAID FIRST METAL OVER THE SECOND DIELECTRIIC LAYER, AND FORMING AN INTERCONNECTION PATTERN IN THE SECOND METALLURGY LAYER WITH UNIFORM WIDTH LINES OVER THE VIA HOLES USING AN ETCHANT SELECTIVE TO SAID SECOND METAL.

Claim 6

A method of fabricating a multi-level interconnection metallurgy system for an integrated semiconductor device comprising forming a first dielectric layer on the surface of a semiconductor substrate, forming a first layer of metal on said first dielectric layer, forming a first metallurgy interconnection pattern having uniform width lines in the first layer of metal by selective removal of portions thereof, depositing a second dielectric layer over the first metallurgy layer and said first dielectric layer, said second dielectric layer of a material dissimilar from said first dielectric layer, forming via holes in said second dielectric layer of a diameter substantially equal to or larger than the width of the underlying conductive lines of the first metallurgy pattern using an Etchant that is selective to the material of the second dielectric layer, forming a second metallurgy interconnection layer with uniform width lines on said second dielectric layer over the via holes by depositing a resist layer on the second dielectric layer, forming a reverse pattern of the interconnection pattern in the resist layer, depositing a blanket second metal layer on the resist layer and exposed portions of the second dielectric layer, subjecting the substrate to an etchant that removes the resist layer thereby removing the resist layer and the overlying portions of the second metal layer but leaving the portions of the metal layer adherent to the second dielectric layer that constitute the second metallurgy interconnection layer.

Claim 7

A method of fabricating a multi-level interconnection metallurgy system for an integrated semiconductor device comprising forming a first dielectric layer on the surface of a semiconductor substrate, forming a first layer of metal on said first dielectric layer, forming a first metallurgy interconnection pattern having uniform width lines in the first layer of metal by selective removal of portions thereof, depositing a second dielectric layer over the first metallurgy layer and said first dielectric layer, said second dielectric layer of a material dissimilar from said first dielectric layer, forming via holes in said second dielectric layer of a diameter substantially equal to or larger than the width of the underlying conductive lines of the first metallurgy pattern using an Etchant that is selective to the material of the second dielectric layer, forming a second metallurgy interconnection layer with uniform width lines on said second dielectric layer over the via holes by depositing a resist layer on the second dielectric layer, forming a reverse pattern of the interconnection pattern in the resist layer, depositing a blanket second metal layer on the resist layer and exposed portions of the second dielectric layer, subjecting the substrate to an etchant that removes the resist layer thereby removing the resist layer and the overlying portions of the second metal layer but leaving the portions of the metal layer adherent to the second dielectric layer that constitute the second metallurgy interconnection layer.