Silicon oxide-silicon nitride coatings for semiconductor devices

Claim 2

The device of claim 1 wherein and said silicon nitride layer is at least approximately 300 A. thick.

Claim 3

The device of claim 1 wherein at least one additional conductive metal member is formed upon said insulating layer and said insulating dielectric layer is sufficiently thin that the application of an electric potential to said additional conductive member is effective to produce an electric field within the surface-adjacent region of said semiconductor wafer to cause signal translation.

Claim 4

A field effect transistor comprising: a. a monocrystalline body of semiconductor material having an active substantially planar major surface and having therein different conductivity-type active major surface-adjacent source and drain regions b. said source and drain regions each defining with the main body of said semiconductor an asymmetrically conductive junction which intersects said major substantially planar surface and mutually defining therebetween a surface-adjacent channel region at the active major substantially planar surface of said body; c. an insulating dielectric layer covering substantially all of said major surface and passivating said junctions; d. a gate member disposed over said channel and operative when properly biased to control electric current conduction through said surface-adjacent channel region; e. contact means extending through said insulating dielectric layer and making electrical contact with restricted portions of said source and drain regions respectively; f. conductive means connected to at least one of said gate member and said souRce and drain contact means and overlying said insulating dielectric layer; g. said insulating dielectric layer comprising: g1. a first insulating passivation layer comprising silicon dioxide formed upon said active major surface of said semiconductor body and covering said junctions and g2. a second alkali metal ion impervious stabilizing layer of amorphous silicon nitride overlying substantially all of said silicon dioxide layer and interposed between said silicon dioxide layer and said conductive means.

Claim 5

The device of claim 5 wherein said silicon dioxide layer is thicker than said silicon nitride layer.

Claim 6

The device of claim 6 wherein said silicon nitride layer is at least approximately 300 A. thick.

Claim 7

A bipolar junction transistor device comprising: a. a monocrystalline wafer of semiconductor material having a major substantially planar active surface; b. emitter collector and base regions respectively located within said wafer and each having a portion thereof adjacent a portion of said active major surface; c. An emitter junction separating said emitter and said base regions and intersecting said active major substantially planar surface; d. A collector junction separating said base and said collector regions and intersecting said major active substantially planar surface; e. An insulating dielectric layer covering substantially all of said active major surface and passivating said junctions; f. Contact members penetrating said insulating dielectric layer and making electric contact electric contact to restricted portions of the surface of at least each of said emitter and said base regions respectively; and g. Conductive means connected to at least one of said contact members and overlying at least a portion of said insulating dielectric layer; h. Said insulating dielectric layer comprising: h1. a first insulating passivating layer comprising silicon dioxide formed upon said active major surface of said semiconductor body and covering said junction; and h2. a second alkali metal ion impervious stabilizing layer of amorphous silicon nitride overlying substantially all of said silicon dioxide layer and interposed between said silicon dioxide layer and said conductive means.

Claim 8

The device of claim 8 wherein said silicon dioxide layer is thicker than said silicon nitride layer.

Claim 9

The device of claim 9 wherein said silicon nitride layer is at least approximately 300 A. thick.

Claim 10

A planar transistor device comprising: a. a body of monocrystalline semiconductor of a one conductivity type having an active substantially planar major surface; b. a base region of different conductivity type diffused into a portion of said semiconductor body adjacent said active major surface, and defining therewith a collector junction which intersects said active major surface; c. an emitter region of one conductivity type diffused only partially into said base region and occupying a portion thereof adjacent said major surface and defining therewith an emitter junction which intersects said active major surface; d. an insulating dielectric layer covering substantially all of said major active surface and passivating said junctions; e. contact means extending through said insulating dielectric layer, and making electrical contact with restricted portions of at least said emitter and base regions respectively; f. conductive means connected to at least one of said contact means and overlying said insulating dielectric layer; g. said insulating dielectric layer comprising: g1. a first insulating passivating layer comprising silicon dioxide formed upon said active major surface of said semiconductor body and covering said junction, and g2. a second alkali metal ion impervious stabilizing layer of amorphous silicon nitride overlying substantially all of said silicon dioxide layer and interposed betwEen said silicon dioxide layer and said conductive means.