Patent US4423337A successfully refreshed from Google Patents.
US4423337A
Expired / Lapsed
US
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Gate circuit for a universal counter
Assignee: Micron Technology Inc
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Filing: 1981-07-13
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Granted: 1983-12-27
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Expires: 2001-07-13
Abstract
Abstract A gating circuit for a universal counter comprises a pair of flip-flops and a pair of logic gates arranged to provide any of a plurality of counting or timing measurements. A gate control circuit includes a control logic unit to provide routing and synchronization of digital signals from several inputs, including an internal source as well as a pair of external sources, into one or both of a pair of count chains.
Inventors
- 👤 William G. Wilke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:49
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K21/00; H03K21/02; H03K21/026
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
132 words
A gating circuit for an electronic counter, comprising: a first bistable control circuit responsive to an arming signal and a first triggering signal for producing a first enable signal, said first triggering signal being selectable from a first input signal and a second input signal; a first gate circuit responsive to said first enable signal for producing a first count signal; means for applying said first input signal to said first gate circuit; a second bistable control circuit responsive to said first enable signal and a second triggering signal for producing a second enable signal, said second triggering signal being selectable from said second input signal and a clock signal; and a second gate circuit responsive to said second enable signal and said second triggering signal for producing a second count signal.
Claim 2
Dependent Claim
132 words
A gating circuit for an electronic counter, comprising: a first bistable control circuit responsive to an arming signal and a first triggering signal for producing a first enable signal, said first triggering signal being selectable from a first input signal and a second input signal; a first gate circuit responsive to said first enable signal for producing a first count signal; means for applying said first input signal to said first gate circuit; a second bistable control circuit responsive to said first enable signal and a second triggering signal for producing a second enable signal, said second triggering signal being selectable from said second input signal and a clock signal; and a second gate circuit responsive to said second enable signal and said second triggering signal for producing a second count signal.
Claim 3
Dependent Claim
51 words
A gating circuit in accordance with claim 1 further comprising logic control means for establishing one of a plurality of operating modes by selectively coupling said first and second input signals, said arming signal, and said clock signal to said bistable control circuits and said gate circuits in a predetermined manner.
Claim 4
Dependent Claim
20 words
A gating circuit in accordance with claim 1 wherein said first and second bistable control circuits comprise triggered flip flops.
Claim 5
Dependent Claim
37 words
A gating circuit in accordance with claim 1 wherein each said count signal is produced in synchronism with a respective triggering signal and on the opposite-slope edge to that used to trigger the respective bistable control circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-26 | 1987-06-27 | 1987-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-26 | 1991-06-27 | 1991-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-26 | 1995-06-27 | 1995-12-27 | $7700.00 | Window Closed / Lapsed |