Voltage comparator using unequal gate width FET's

Claim 1

An apparatus for detecting the amplitude of an input signal relative to a predetermined threshold voltage, said apparatus comprising: first and second field effect transistors (FET's), each having gate, source and drain electrodes; said first FET having its gate electrode coupled to its source electrode, and having a first gate electrode width to provide with a potential across said first FET a predetermined reference load current level through said first FET establishing said predetermined threshold voltage; said second FET having a second gate electrode width greater than said first width to thereby provide with a potential across said second FET, in response to a range of values of said input signal to said second FET gate electrode, a corresponding range of saturation current levels above and below said load current; said first and said second FET's connected in series across a source of potential; and means for coupling said input signal to said second FET gate electrode whereby when said input signal changes from a value which produces a saturation current level through said second FET above said load current to a value which produces a saturation current level through said second FET below said load current the output level across said second FET changes.

Claim 2

An apparatus for detecting the amplitude of an input signal relative to a predetermined threshold voltage, said apparatus comprising: first and second field effect transistors (FET's), each having gate, source and drain electrodes; said first FET having its gate electrode coupled to its source electrode, and having a first gate electrode width to provide with a potential across said first FET a predetermined reference load current level through said first FET establishing said predetermined threshold voltage; said second FET having a second gate electrode width greater than said first width to thereby provide with a potential across said second FET, in response to a range of values of said input signal to said second FET gate electrode, a corresponding range of saturation current levels above and below said load current; said first and said second FET's connected in series across a source of potential; and means for coupling said input signal to said second FET gate electrode whereby when said input signal changes from a value which produces a saturation current level through said second FET above said load current to a value which produces a saturation current level through said second FET below said load current the output level across said second FET changes.

Claim 4

An apparatus for converting the instantaneous amplitude of an input analog signal to a digital representation of that level, said apparatus comprising: a plurality of voltage comparators each comprising a first and a second FET connected in series across a source of potential, each of said first FET's including a gate electrode of a first width to thereby provide a first saturation current level in response to a first value of said input signal at said gate electrode and a second different saturation current level in response to a second value of said input signal at said gate electrode, said first width of said gate electrodes being substantially identical for each of said plurality of said first FET's to thereby provide substantially identical first and second saturation current levels for each of said plurality of said first FET's; each of said second FET's having its gate electrode coupled to its source electrode, said gate electrodes of said second FET's having a second width smaller than said first width to thereby provide predetermined reference load current levels through each of said plurality of voltage comparators between said first and said second saturation current levels, said second widths being different for each of said plurality of second FET's to thereby provide load current levels which are different for each of said plurality of second FET's; and means for coupling said input signal to each of said gate electrodes of said plurality of first FET's whereby as the voltage level of said input signal is varied between said first and said second values, the voltage level across each of said first FET's shifts between a first value and a second value at different input levels.

Claim 5

An apparatus for converting the instantaneous amplitude of an input analog signal to a digital representation of that level, said apparatus comprising: a plurality of voltage comparators each comprising a first and a second FET connected in series across a source of potential, each of said first FET's including a gate electrode of a first width to thereby provide a first saturation current level in response to a first value of said input signal at said gate electrode and a second different saturation current level in response to a second value of said input signal at said gate electrode, said first width of said gate electrodes being substantially identical for each of said plurality of said first FET's to thereby provide substantially identical first and second saturation current levels for each of said plurality of said first FET's; each of said second FET's having its gate electrode coupled to its source electrode, said gate electrodes of said second FET's having a second width smaller than said first width to thereby provide predetermined reference load current levels through each of said plurality of voltage comparators between said first and said second saturation current levels, said second widths being different for each of said plurality of second FET's to thereby provide load current levels which are different for each of said plurality of second FET's; and means for coupling said input signal to each of said gate electrodes of said plurality of first FET's whereby as the voltage level of said input signal is varied between said first and said second values, the voltage level across each of said first FET's shifts between a first value and a second value at different input levels.