Patent US4419818A successfully refreshed from Google Patents.
US4419818A
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US
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Method for manufacturing substrate with selectively trimmable resistors between signal leads and ground structure
Assignee: TE Connectivity Corp
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Filing: 1981-10-26
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Granted: 1983-12-13
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Expires: 2001-10-26
Abstract
Abstract Technique for terminating signal leads on a substrate for a semiconductor chip to discrete resistors to eliminate impedance discontinuities involves a substrate having signal leads connected to resistive material which is in turn connected to a ground bus. Laser trimming equipment is used to selectively disconnect signal leads from the resistor zone, or to create separate resistor paths for each signal lead to bus, while trimming the resistor to the required transmission line terminating value. The signal leads are connected to the semiconductor chip by elevated leads which pass over the resistive material and the ground bus.
Inventors
- 👤 Dimitry G. Grabbe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:56
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/401; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49146; Y10T29/49155; Y10T29/49156; Y10T29/49162
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
112 words
A method of manufacturing a semiconductor chip carrier comprising the steps of: (a) providing a dielectric substrate; (b) bonding signal leads and at least one ground bus on said substrate; (c) bonding resistive material on said substrate connected between said signal leads and said ground bus; (d) selectively removing said resistive material to form discrete paths of desired resistance between at least some of said signal leads and said ground bus, (e) placing a semiconductor chip on said substrate adjacent said ground bus; and (f) connecting at least some of said signal leads to said semiconductor chip by means of an elevated conductor passing over said resistive material and said ground bus.
Claim 2
Independent Claim
112 words
A method of manufacturing a semiconductor chip carrier comprising the steps of: (a) providing a dielectric substrate; (b) bonding signal leads and at least one ground bus on said substrate; (c) bonding resistive material on said substrate connected between said signal leads and said ground bus; (d) selectively removing said resistive material to form discrete paths of desired resistance between at least some of said signal leads and said ground bus, (e) placing a semiconductor chip on said substrate adjacent said ground bus; and (f) connecting at least some of said signal leads to said semiconductor chip by means of an elevated conductor passing over said resistive material and said ground bus.
Claim 3
Dependent Claim
38 words
A method as in claim 1 wherein a power bus is bonded on said substrate between said ground bus and said semiconductor chip, said elevated conductors passing over said resistive material, said ground bus, and said power bus.
Claim 4
Dependent Claim
14 words
A method as in claim 1, wherein said ground bus substantially surrounds said chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-12 | 1987-06-13 | 1987-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-12 | 1991-06-13 | 1991-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-12 | 1995-06-13 | 1995-12-13 | $7700.00 | Window Closed / Lapsed |