Self-aligned field effect transistor process

Abstract

Abstract A method for fabricating a semiconductor [integrated circuit] structure having a sub-micrometer gate length field effect transistor device is described. An isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistors [devices]. A heavily doped conductive layer and an insulator layer are formed thereover. The multilayer structure is etched to result in a patterned conductive layer having substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings in the pattern at the location of the field effect transistor channel. The pattern in the source/drain areas extend over the isolation pattern. A controlled sub-micrometer thickness insulating layer is formed on these vertical sidewalls. The sidewall insulating layer is utilized to controllably reduce the channel length of the field effect transistor. [The sidewall layer is preferably doped with conductive imparting impurities.] The gate dielectric is formed on the channel surface. The source/drain regions [and preferably lightly doped region] are [simultaneously] formed by thermal drive-in from the conductive layer [and sidewall insulating layer respectively]. The desired gate electrode is formed upon the gate dielectric and electrical connections made to the various elements of the field effect transistor devices. [The conductive layer and resulting contacts to said source/drain regions may be composed of polycrystalline silicon, metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.]

Inventors

• 👤 Jacob Riseman

Bibliographic Details