Radiation hardened accessible memory

Claim 2

In combination with a bistable device comprised of N and P-type devices, and having first and second input terminals, and responsive to high and low level signals or to low and high level signals supplied to said first and second input terminals, respectively, to assume its first or second state, respectively, accessing means for supplying high and low signal levels or low and high signal levels to said first and second input terminals, respectively, and comprising: first and second P-type devices each having a drain electrode connected to one of said input terminals, a source electrode, and a gate electrode, and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal, respectively, to said one of said input terminals; means for generating a control signal having first and second levels; logic means responsive to the first level of said control signal to generate and supply said enabling and disabling signals to said first and second P-type devices respectively, and responsive to said second level of said control signal to generate and supply said enabling and disabling signals to said second and first P-type devices, respectively; means for supplying a reference potential to the gate electrodes of said first and second P-type devices when said enabling and disabling voltages are supplied to said first and second P-type devices; and means for sensing the state of said bistable device comprising: capacitor means connected between said source electrodes of said first and second P-type devices and said reference potential; and means for detecting the potential across said capacitor means during a time period between successive level changes of said control signal.

Claim 3

In combination with a bistable device comprised of N and P-type devices, having at least one input terminal, and responsive to high and low level signals supplied to said at least one input terminal to assume its first or second state, respectively, accessing means for supplying said high and low signal levels to said at least one input terminal and comprising: a second P-type device having a drain electrode connected to said at least one input terminal, a source electrode, a gate electrode, and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal, respectively, to said at least one input terminal; means for generating a control signal having first and second levels; logic means responsive to the first level of said control signal to generate and supply said enabling signal to said second P-type device and responsive to the second level of said control signal to generate and supply said disabling signal to said second P-type device; means for supplying a reference potential to the gate electrode of said second P-type device when said enabling or disabling voltages are supplied to said second P-type device; and means for sensing the state of said bistable device comprising; capacitor means connected between said source electrode of said second P-type device and said reference potential; and means for detecting the potential across said capacitor means during a time period between successive level changes of said control signal.

Claim 4

In combination with a bistable device comprised of N and P-type devices, having at least one input terminal, and responsive to high and low level signals supplied to said at least one input terminal to assume its first or second state, respectively, accessing means for supplying said high and low signal levels to said at least one input terminal and comprising: a second P-type device having a drain electrode connected to said at least one input terminal, a source electrode, a gate electrode, and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal, respectively, to said at least one input terminal; means for generating a control signal having first and second levels; logic means responsive to the first level of said control signal to generate and supply said enabling signal to said second P-type device and responsive to the second level of said control signal to generate and supply said disabling signal to said second P-type device; means for supplying a reference potential to the gate electrode of said second P-type device when said enabling or disabling voltages are supplied to said second P-type device; and means for sensing the state of said bistable device comprising; capacitor means connected between said source electrode of said second P-type device and said reference potential; and means for detecting the potential across said capacitor means during a time period between successive level changes of said control signal.

Claim 5

In combination with a bistable device comprising N and P-type devices, having at least one input terminal, and responsive to high and low level signals supplied to said at least one input terminal to assume its first or second state, respectively, accessing means for selectively supplying said high and low levels to said at least one input terminal and comprising: a second P-type device having a drain electrode connected to said at least one input terminal, a source electrode, and a gate electrode and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal, respectively, to said at least one input terminal; means for generating and supplying said enabling and disabling signals to said second P-type device during predetermined time intervals; means for supplying a reference potential to said gate electrode during said predetermined time interval; means for storing the potential difference between said reference potential and said enabling or disabling signals; and means for detecting said potential difference at predetermined times.

Claim 6

In combination with a bistable device comprising N and P-type devices, having at least one input terminal, and responsive to high and low level signals supplied to said at least one input terminal to assume its first or second state, respectively, accessing means for selectively supplying said high and low levels to said at least one input terminal and comprising: a second P-type device having a drain electrode connected to said at least one input terminal, a source electrode, and a gate electrode and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal, respectively, to said at least one input terminal; means for generating and supplying said enabling and disabling signals to said second P-type device during predetermined time intervals; means for supplying a reference potential to said gate electrode during said predetermined time interval; means for storing the potential difference between said reference potential and said enabling or disabling signals; and means for detecting said potential difference at predetermined times.

Claim 7

A radiation resistant solid-state memory device comprising: a storage means having first and second states representing storage of a binary 1 or a binary 0, respectively; first and second input terminals; said storage means responsive to high and low level signals supplied to said first and second input terminals, respectively, to assume its first or second state, respectively; accessing means for supplying high and low signal levels to said first and second input terminals, respectively, and to said second and first input terminals, respectively, comprising first and second P-type devices each having a drain electrode connected to one of said input terminals, a source electrode, and a gate electrode and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal to said one of said input terminals; means for generating a control signal having first and second levels; and logic means responsive to said first level of said control signal to supply said enabling and disabling signals to said first and second P-type devices, respectively, and responsive to said second level of said control signal to supply said enabling and disabling signals to said second and first P-type devices, respectively; and means for sensing the state of said bistable memory device during a time period between successive level changes of said control signals comprising; means for supplying a reference potential to the gate electrodes of said P-type devices when said enabling and disabling voltages are supplied to said P-type devices; capacitor means connected between said source electrodes of said P-type devices and said reference potential; and means for detecting the potential across said capacitor means during the time period between successive changes of said control signal.

Claim 8

A radiation resistant solid-state memory device comprising: a storage means having first and second states representing storage of a binary 1 or a binary 0, respectively; first and second input terminals; said storage means responsive to high and low level signals supplied to said first and second input terminals, respectively, to assume its first or second state, respectively; accessing means for supplying high and low signal levels to said first and second input terminals, respectively, and to said second and first input terminals, respectively, comprising first and second P-type devices each having a drain electrode connected to one of said input terminals, a source electrode, and a gate electrode and responsive to enabling and disabling voltages applied across said gate electrode and said source electrode to supply said high level signal or said low level signal to said one of said input terminals; means for generating a control signal having first and second levels; and logic means responsive to said first level of said control signal to supply said enabling and disabling signals to said first and second P-type devices, respectively, and responsive to said second level of said control signal to supply said enabling and disabling signals to said second and first P-type devices, respectively; and means for sensing the state of said bistable memory device during a time period between successive level changes of said control signals comprising; means for supplying a reference potential to the gate electrodes of said P-type devices when said enabling and disabling voltages are supplied to said P-type devices; capacitor means connected between said source electrodes of said P-type devices and said reference potential; and means for detecting the potential across said capacitor means during the time period between successive changes of said control signal.