US3644907A
Expired / Lapsed
US
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Complementary mosfet memory cell
Assignee: Westinghouse Electric Corp
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Filing: 1969-12-31
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Granted: 1972-02-22
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Expires: 1989-12-31
Abstract
Abstract A semiconductor read/write memory array and memory cell therefore including complementary metal oxide semiconductor field-effect transistors (MOSFETs) coupled together as a first and a second inverter circuit with direct cross-coupled connections therebetween for providing a flip-flop circuit. Each bit of the memory array is comprised of at least five MOSFET devices operated from a single clocked power supply source wherein four of the MOSFET devices are operated as complementary pairs to comprise the first and second inverters. The flip-flop circuit is clocked or pulsed for turning the MOSFET devices ''''off'''' of one of the inverters referred to as the output inverter to trap an electrical charge at one of the circuit nodes in order to obtain a high input impedance so that the state of the cell can be changed when addressed or alternatively to preset the logic output state of the memory cell. The memory cell is coupled to a common input/output digit data line and an address line of the memory array by means of a selection switch MOSFET so that data is written into and read out of the memory cell on the same digit data line through the selection switch MOSFET when turned ''''on'''' by means of a signal applied to the address line. Furthermore, nondestructive readout of the state of the memory cell when addressed is achieved by precharging the digit data line to a predetermined potential prior to the energization of the selection switch MOSFET during the read mode.
Inventors
- 👤 James R Gricchi
- 👤 James R Hudson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:48
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/401; G11C11/402; G11C11/4023; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
359 words
The combination comprising: a binary memory cell operable in a read and write mode and comprised of a first and a second binary logic inverter circuit each having an input and an output terminal; first circuit means directly connecting the output terminal of said first inverter circuit to the input terminal of said second inverter circuit and defining a first circuit node thereat; second circuit means directly connecting the input terminal of said first inverter circuit to the output terminal of said second inverter circuit and defining a second circuit node thereat, said first and said second circuit nodes additionally including a first and a second node capacitance respectively which is adapted to be charged or discharged in accordance with the binary logic state of said first and second inverter; clock circuit means providing at least a first and a second synchronized clock voltage signal; means coupling said clock circuit means to at least one Inverter circuit of said first and said second inverter circuits for applying said first clock voltage signal thereto for altering the conductive state of one inverter circuit during a first portion of the write mode to selectively constrain the voltage at said first circuit node to a predetermined voltage level; memory cell-addressing means having a signal applied thereto indicative of a nonaddress and an address command during said read and write mode of operation; common input/output data-transfer means having a signal applied thereto indicative of a first and a second binary logic level during said read and write mode of operation; memory cell-selection switch means, connected to and operated by said addressing means, coupled between said common input/output data-transfer means and said first circuit node of said memory cell, being energized by said addressing means to connect said first circuit node to said input/output data means; and means coupled to said clock circuit means and said common input/output data-transfer means and responsive to said second clock voltage signal from said clock circuit means for selectively establishing a predetermined charge state on said input/output data-transfer means during a first portion of the read mode of operation prior to the energization of said selection switch means.
Claim 2
Dependent Claim
359 words
The combination comprising: a binary memory cell operable in a read and write mode and comprised of a first and a second binary logic inverter circuit each having an input and an output terminal; first circuit means directly connecting the output terminal of said first inverter circuit to the input terminal of said second inverter circuit and defining a first circuit node thereat; second circuit means directly connecting the input terminal of said first inverter circuit to the output terminal of said second inverter circuit and defining a second circuit node thereat, said first and said second circuit nodes additionally including a first and a second node capacitance respectively which is adapted to be charged or discharged in accordance with the binary logic state of said first and second inverter; clock circuit means providing at least a first and a second synchronized clock voltage signal; means coupling said clock circuit means to at least one Inverter circuit of said first and said second inverter circuits for applying said first clock voltage signal thereto for altering the conductive state of one inverter circuit during a first portion of the write mode to selectively constrain the voltage at said first circuit node to a predetermined voltage level; memory cell-addressing means having a signal applied thereto indicative of a nonaddress and an address command during said read and write mode of operation; common input/output data-transfer means having a signal applied thereto indicative of a first and a second binary logic level during said read and write mode of operation; memory cell-selection switch means, connected to and operated by said addressing means, coupled between said common input/output data-transfer means and said first circuit node of said memory cell, being energized by said addressing means to connect said first circuit node to said input/output data means; and means coupled to said clock circuit means and said common input/output data-transfer means and responsive to said second clock voltage signal from said clock circuit means for selectively establishing a predetermined charge state on said input/output data-transfer means during a first portion of the read mode of operation prior to the energization of said selection switch means.
Claim 3
Dependent Claim
64 words
The invention as defined by claim 1 wherein said first and second binary logic inverter circuit is each comprised of a pair of complementary field-effect semiconductor devices having an input terminal and a pair of output terminals and including circuit means commonly connecting the input terminals of each pair together and one like output terminal of each of said pair of output terminals together.
Claim 4
Dependent Claim
40 words
The invention as defined by claim 2 wherein said field-effect semiconductor devices are comprised of metal oxide semiconductor field-effect transistors wherein said input terminal comprises the gate terminal and said pair of output terminals comprises the source and drain terminals.
Claim 5
Dependent Claim
124 words
The invention as defined by claim 1 including means coupling said clock means to both inverter circuits of said first and second inverters as a power supply voltage, and circuit means returning both inverters to a point of reference potential, said first clock voltage signal changing to a level during said first portion of the write mode prior to the energization of said addressing means to selectively trap a charge on one node capacitance of said first and second node capacitance to render said first and second inverter nonconductive and thereby providing a relatively high impedance at said first circuit node so that the logic state of said memory cell can be easily changed during said write mode when said addressing means is energized.
Claim 6
Dependent Claim
92 words
The invention as defined by claim 4 wherein said first and second inverter circuits are comprised of a first and second pair of complementary field-effect transistors each having gate, source, and drain terminals; circuit means commonly coupling said gate terminals of each pair together and the drain terminal of each pair together and wherein said clock voltage signal is commonly applied to like source terminals of both pairs of field-effect transistors; and circuit means coupling the opposite like source terminals of said first and second pairs to said point of reference potential.
Claim 7
Dependent Claim
53 words
The invention as defined by claim 5 and wherein said selection switch means comprises another field-effect transistor having gate, source, and drain terminals and additionally including means coupling the source and drain terminals between said first circuit node and said common input/output data-transfer means, and said gate terminal to said memory cell-addressing means.
Claim 8
Dependent Claim
72 words
The invention as defined by claim 6 and wherein said means for selectively establishing a predetermined charge state on said input/output data-transfer means comprises still another field-effect transistor having gate, source, and drain terminals including circuit means for coupling said second clock voltage signal from said clock circuit means to said gate terminal, and circuit means coupling said source and drain terminals between a predetermined voltage and said common input/output data-transfer means.
Claim 9
Dependent Claim
24 words
The invention as defined by claim 7 wherein said another and said still another field-effect transistor comprise field-effect transistors of mutually opposite type semiconductivity.
Claim 10
Dependent Claim
67 words
The invention as defined by claim 8 wherein said still another field-effect transistor comprises a P-channel device and wherein said drain terminal is coupled to a positive voltage supply and said source terminal is coupled to said common input/output data-transfer means whereby said input/output data-transfer means is precharged to a positive potential prior to the energization of said another field-effect transistor during said read mode of operation.
Claim 11
Dependent Claim
17 words
The invention as defined by claim 9 wherein all field-effect transistors comprise metal oxide semiconductor field-effect transistors.
Claim 12
Dependent Claim
138 words
The invention as defined by claim 1 wherein said first and second binary inverter circuits are each comprised of a pair of complementary field-effect transistors having base, source and drain terminals, and including means mutually coupling said gate terminals of each pair together and said drain terminals of each pair together and wherein said first clock voltage signal of said clock circuit means is applied to one of said source terminals of one pair of complementary field-effect transistors and including circuit means coupling a point of reference potential to the other source terminal of said one pair of field-effect transistors; and a constant supply potential connected to one source terminal of the other pair of field-effect transistors including circuit means coupling the other source terminal of said other pair of field-effect transistors to said point of reference potential.
Claim 13
Dependent Claim
104 words
The invention as defined by claim 11 and wherein said means for establishing a predetermined charge state on said input/output data-transfer means comprises a field-effect transistor having a gate, source and drain terminals including circuit means coupling said second clock voltage signal from said clock circuit means to said gate terminal and circuit means coupling said drain and source terminals between said point of reference potential and said input/output data-transfer means, being rendered conductive by said second clock voltage signal to establish a substantially zero-charge state on said input/output data-transfer means prior to the energization of said selection switch means during said read mode.
Claim 14
Dependent Claim
182 words
The invention as defined by claim 1 wherein said first and second binary inverter circuits are each comprised of a pair of complementary field-effect transistors having gate, source and drain terminals including circuit means for coupling said gate terminals of each pair of transistors together and said drain terminals of each pair of transistors together; circuit means coupling one like source terminal of each of said pair of transistors to a point of reference potential; a source of fixed power supply potential commonly coupled to the other like source terminal of each of said pair of transistors; another field-effect transistor having gate, source, and drain terminals including circuit means for connecting the drain and source terminals thereof commonly to the respective source and drain terminals of the transistor of said complementary pair of transistors of said second inverter stage having like semiconductivity; and circuit means coupling said first clock voltage signal of said clock circuit means to the gate terminal of said another transistor for selectively presetting the binary logic state of said first circuit node to a predetermined digital logic level.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-21 | 1975-08-23 | 1976-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-21 | 1979-08-23 | 1980-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-21 | 1983-08-23 | 1984-02-22 | $7700.00 | Window Closed / Lapsed |