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US4417315A
Expired / Lapsed
US
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Method and apparatus for incrementing a digital word
Assignee: Boeing North American Inc
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Filing: 1981-07-14
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Granted: 1983-11-22
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Expires: 2001-07-14
Abstract
Abstract A circuit is presented designed specifically for use in complementary symmetry design techniques such as CMOS/SOS wherein inverting gate types are a preferred design. This design is obtained with a minimum of delay by changing gate types in the ripple carry path wherein alternating stages utilize NAND gates with the remaining ripple carry path stages using NOR gates. To accomplish this approach, the bit stages of the word utilizing the NOR gates must have the bits inverted before being applied to the incrementing circuit.
Inventors
- 👤 Jeffrey D. Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
174 words
Logic apparatus comprising, in combination: carry input means for providing a carry input signal; input means for providing N stage input signals and (N+1) stage input signals; NAND gate means and first exclusive OR gate means, each including output means, connected to said carry input signal means and to said input means for receiving carry input signals and N stage input signals respectively; N stage SUM output means connected to said output of said first exclusive OR gate means for providing N stage SUM output signals; inverter means connected to said input signals means for receiving said (N+1) stage input signals and providing a logically inverted output therefrom at output means thereof; NOR gate means connected to said NAND means and to said inverter means for logically NORing the inputs and providing a carry output signal at an output means thereof; and second exclusive OR gate means connected to said inverter means and to said output of said NAND means for logically exclusively combining said inputs to provide an (N+1) stage SUM output signal.
Claim 2
Dependent Claim
174 words
Logic apparatus comprising, in combination: carry input means for providing a carry input signal; input means for providing N stage input signals and (N+1) stage input signals; NAND gate means and first exclusive OR gate means, each including output means, connected to said carry input signal means and to said input means for receiving carry input signals and N stage input signals respectively; N stage SUM output means connected to said output of said first exclusive OR gate means for providing N stage SUM output signals; inverter means connected to said input signals means for receiving said (N+1) stage input signals and providing a logically inverted output therefrom at output means thereof; NOR gate means connected to said NAND means and to said inverter means for logically NORing the inputs and providing a carry output signal at an output means thereof; and second exclusive OR gate means connected to said inverter means and to said output of said NAND means for logically exclusively combining said inputs to provide an (N+1) stage SUM output signal.
Claim 3
Independent Claim
52 words
The method of incrementing an N bit logic word comprising the steps of: alternately NANDing and NORing carry input signals with stage bit signals in a ripple carry path; inverting stage bit input signals for NOR bit stages; and XORing carry and stage signals to provide stage SUM logic value output signals.
Claim 4
Independent Claim
52 words
The method of incrementing an N bit logic word comprising the steps of: alternately NANDing and NORing carry input signals with stage bit signals in a ripple carry path; inverting stage bit input signals for NOR bit stages; and XORing carry and stage signals to provide stage SUM logic value output signals.
Claim 5
Dependent Claim
198 words
Apparatus for incrementing an N bit logic word comprising, in combination; signal supply means for supplying N bit stages of logic bit value signals first means, including signal and carry input means, for logically NANDing inputs in alternate stages of said apparatus; second means, including signal and carry input means, for logically NORing inputs in the remaining stages of said apparatus, a serial logic path being formed thereby; third means connecting said first means and said second means together for supplying carry output signals from each bit stage to the carry input of the following bit stage; fourth means, connected to said first means, for supplying a logic value input to said carry input means of the first stage of said apparatus; means, for inverting the input signal from said signal supply means, connected to said signal supply means and to said signal input means for each of the stages including said second means; and means, connected to said first means and said second means, for exclusive ORing stage input signal logic values as applied to the serial logic path and carry input signals in each stage of the word to provide stage SUM logic value output signals.
Claim 6
Dependent Claim
198 words
Apparatus for incrementing an N bit logic word comprising, in combination; signal supply means for supplying N bit stages of logic bit value signals first means, including signal and carry input means, for logically NANDing inputs in alternate stages of said apparatus; second means, including signal and carry input means, for logically NORing inputs in the remaining stages of said apparatus, a serial logic path being formed thereby; third means connecting said first means and said second means together for supplying carry output signals from each bit stage to the carry input of the following bit stage; fourth means, connected to said first means, for supplying a logic value input to said carry input means of the first stage of said apparatus; means, for inverting the input signal from said signal supply means, connected to said signal supply means and to said signal input means for each of the stages including said second means; and means, connected to said first means and said second means, for exclusive ORing stage input signal logic values as applied to the serial logic path and carry input signals in each stage of the word to provide stage SUM logic value output signals.
Claim 7
Independent Claim
98 words
The method of incrementing an n bit logic word comprising the steps of: inverting alternately occurring bits in an n bit logic word; serially NANDing the non-inverted inputs with carry input signals and outputting from the NANDing means a carry out signal for each of n/2 bit stages of said n bit logic word; logically NORing the inverted logic bits with received carry out signals for each of the remaining bit stages; and exclusively ORing the signals being NANDed or NORed in an individual stage to form a SUM output signal for that stage in the incrementation process.
Claim 8
Independent Claim
98 words
The method of incrementing an n bit logic word comprising the steps of: inverting alternately occurring bits in an n bit logic word; serially NANDing the non-inverted inputs with carry input signals and outputting from the NANDing means a carry out signal for each of n/2 bit stages of said n bit logic word; logically NORing the inverted logic bits with received carry out signals for each of the remaining bit stages; and exclusively ORing the signals being NANDed or NORed in an individual stage to form a SUM output signal for that stage in the incrementation process.
Claim 9
Dependent Claim
168 words
Apparatus for incrementing the logic value of a multiple bit word containing N bit stages comprising, in combination: first means for inputting a signal representative of each bit of a multiple bit word to be incremented wherein every other bit in increasing numerical weight is inverted in logic value; second means, connected to said first means and to a logically previous stage in the apparatus, for logically NANDing the non-inverted bits with a carry input from the logically previous stage for supplying a carry output signal; third means, connected to said first means and to said second means, for logically NORing the inverted input bits with the received carry input signal for that stage and providing a carry output for use in an immediately subsequent bit stage; and fourth means for exclusively combining the logic values of each of the signals supplied to the NAND or NOR means for each stage to provide as an output a logic value for that associated bit position of the incremented word.
Claim 10
Dependent Claim
168 words
Apparatus for incrementing the logic value of a multiple bit word containing N bit stages comprising, in combination: first means for inputting a signal representative of each bit of a multiple bit word to be incremented wherein every other bit in increasing numerical weight is inverted in logic value; second means, connected to said first means and to a logically previous stage in the apparatus, for logically NANDing the non-inverted bits with a carry input from the logically previous stage for supplying a carry output signal; third means, connected to said first means and to said second means, for logically NORing the inverted input bits with the received carry input signal for that stage and providing a carry output for use in an immediately subsequent bit stage; and fourth means for exclusively combining the logic values of each of the signals supplied to the NAND or NOR means for each stage to provide as an output a logic value for that associated bit position of the incremented word.
Claim 11
Dependent Claim
16 words
Apparatus as claimed in claim 5 wherein the exclusive logic combining is an exclusive OR function.
Claim 12
Independent Claim
104 words
The method of incrementing a multiple bit digital word comprising the steps of: exclusive ORing each of a multiplicity of alternate bit positions of a word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals; exclusive NORing each of the remaining bit positions of the word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals; NANDing each set of signals exclusively ORed for providing carry signals to a subsequent stage; and ANDing each set of signals exclusively NORed for providing carry signals to a subsequent stage.
Claim 13
Independent Claim
104 words
The method of incrementing a multiple bit digital word comprising the steps of: exclusive ORing each of a multiplicity of alternate bit positions of a word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals; exclusive NORing each of the remaining bit positions of the word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals; NANDing each set of signals exclusively ORed for providing carry signals to a subsequent stage; and ANDing each set of signals exclusively NORed for providing carry signals to a subsequent stage.
Claim 14
Independent Claim
146 words
The method of incrementing a digital word comprising a plurality of data bit positions comprising the steps of: exclusive ORing data bits from each alternate one of said plurality of data bit positions of a word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals representative in bit position of the data bits input to be exclusively ORed; exclusive NORing data bits received from remaining bit positions of the word to be incremented with carry signals from the previous stage to provide corresponding data bit position output signals; NANDing each set of signals exclusively ORed for providing carry signals to a subsequent data bit position stage; and NORing signals supplied to each bit position stage, having an exclusive NORing step, after inversion of the data signal for providing carry signals to a subsequent data bit position stage.
Claim 15
Independent Claim
146 words
The method of incrementing a digital word comprising a plurality of data bit positions comprising the steps of: exclusive ORing data bits from each alternate one of said plurality of data bit positions of a word to be incremented with carry signals from associated logically previous stages to provide data bit position output signals representative in bit position of the data bits input to be exclusively ORed; exclusive NORing data bits received from remaining bit positions of the word to be incremented with carry signals from the previous stage to provide corresponding data bit position output signals; NANDing each set of signals exclusively ORed for providing carry signals to a subsequent data bit position stage; and NORing signals supplied to each bit position stage, having an exclusive NORing step, after inversion of the data signal for providing carry signals to a subsequent data bit position stage.
Claim 16
Dependent Claim
127 words
Apparatus for incrementing a digital word comprising, in combination: means for providing data bit signals representative of adjacent first and second data bit positions of a word to be incremented; means for supplying a first serial path signal which serial path signal acts as a carry signal; means for exclusive ORing said serial path signal with said first data bit position signal to provide a first stage output signal; means for NANDing the signals exclusively ORed to provide a second serial path signal; means for exclusive NORing the second data bit position signal with the second serial path signal for providing a second stage output signal in a word to be incremented; and means for ANDing the signals exclusively NORed to provide a third serial path signal.
Claim 17
Dependent Claim
127 words
Apparatus for incrementing a digital word comprising, in combination: means for providing data bit signals representative of adjacent first and second data bit positions of a word to be incremented; means for supplying a first serial path signal which serial path signal acts as a carry signal; means for exclusive ORing said serial path signal with said first data bit position signal to provide a first stage output signal; means for NANDing the signals exclusively ORed to provide a second serial path signal; means for exclusive NORing the second data bit position signal with the second serial path signal for providing a second stage output signal in a word to be incremented; and means for ANDing the signals exclusively NORed to provide a third serial path signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-21 | 1987-05-23 | 1987-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-21 | 1991-05-23 | 1991-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-21 | 1995-05-23 | 1995-11-22 | $7700.00 | Window Closed / Lapsed |