Transistor-transistor-logic circuits having improved breakdown protection circuitry

Claim 2

In a logic circuit having input means for receiving one or more binary logic signals, an output transistor having base, emitter, and collector terminals, an output terminal coupled to said collector terminal of said output transistor, and a current drive transistor coupled between the input means and the output transistor for providing turn on drive current for the output transistor when binary logic signals concurrently applied to the input means reach a determined logic level, the improvement comprising: a turn off drive transistor having an emitter, a base and a collector, said emitter of said turn off drive transistor being coupled to said emitter of said output transistor; a first resistor coupled between said collector of said turn off drive transistor and the base of said output transistor;

Claim 3

a second resistor coupled between the base of said turn off drive transistor and the base of said output transistor, said turn off drive transistor and said first and second resistors providing a discharge path from the output transistor when the latter is turned on; and means coupled to said turn off drive transistor for sourcing leakage current away from said output transistor so as to prevent said output transistor from turning on due to said leakage current.

Claim 4

a second resistor coupled between the base of said turn off drive transistor and the base of said output transistor, said turn off drive transistor and said first and second resistors providing a discharge path from the output transistor when the latter is turned on; and means coupled to said turn off drive transistor for sourcing leakage current away from said output transistor so as to prevent said output transistor from turning on due to said leakage current.

Claim 5

A logic circuit according to claim 1 wherein said means comprises a third resistor coupled in parallel with the collector-emitter path of said turn off drive transistor.

Claim 6

A circuit according to claim 2 wherein said third resistor has a resistance substantially larger than that of said first resistor.

Claim 7

In a circuit configuration employing a first transistor having base, emitter and collector electrodes and means for biasing said first transistor into conduction and means for turning off said first transistor, an output terminal coupled to said collector electrode of said first transistor, whereby the emitter electrode of said first transistor is connectible to a reference potential, the improvement comprising: second transistor means having base, emitter and collector electrodes; first current limiting means intermediate said collector electrode of said second transistor and said base electrode of said first transistor; second current limiting means intermediate said base electrode of said second transistor and said base electrode of said first transistor, the emitter electrode of said second transistor being connectible to said reference potential whereby said second transistor means and said current limiting means provide a discharge path from said base electrode of said first transistor when said first transistor is turned off by said turn off means; and third current limiting means connectible between said collector electrode of said second transistor and said reference potential for providing a current path to said reference potential for leakage current in said first transistor to prevent said first transistor from being turned on by said leakage current.

Claim 8

In a circuit configuration employing a first transistor having base, emitter and collector electrodes and means for biasing said first transistor into conduction and means for turning off said first transistor, an output terminal coupled to said collector electrode of said first transistor, whereby the emitter electrode of said first transistor is connectible to a reference potential, the improvement comprising: second transistor means having base, emitter and collector electrodes; first current limiting means intermediate said collector electrode of said second transistor and said base electrode of said first transistor; second current limiting means intermediate said base electrode of said second transistor and said base electrode of said first transistor, the emitter electrode of said second transistor being connectible to said reference potential whereby said second transistor means and said current limiting means provide a discharge path from said base electrode of said first transistor when said first transistor is turned off by said turn off means; and third current limiting means connectible between said collector electrode of said second transistor and said reference potential for providing a current path to said reference potential for leakage current in said first transistor to prevent said first transistor from being turned on by said leakage current.

Claim 9

A circuit according to claim 4 wherein said first and third current limiting means are resistors and wherein said third current limiting means has a resistance substantially greater than that of said first current limiting means.

Claim 10

A transistor transistor logic circuit including in combination: input means for receiving binary logic signals; at least one output transistor having base, emitter and collector terminals; at least one current drive transistor having emitter, base and collector terminals with the base-emitter path thereof coupled between said input means and the base of said at least one output transistor, said one current drive transistor providing a turn-on drive current for said one output transistor when binary logic signals concurrently applied to said input means reach a predetermined logical level; resistance means being connectible between a voltage supply terminal and respective ones of said input means, said one current drive transistor, and said one output transistor for biasing same and biasing said one output transistor and said one current drive transistor non-conducting in the absence of binary logic signals at a predetermined logic level concurrently applied to said input means; a discharge circuit means including a transistor having its base and collector regions resistively connected to the base of said one output transistor and its emitter being connectible to a reference potential said collector region also being resistively coupled to said reference potential for supplying a current conducting path for leakage current in said at least one output transistor so as to prevent said at least one output transistor from turning on due to said leakage current.

Claim 11

A transistor transistor logic circuit including in combination: input means for receiving binary logic signals; at least one output transistor having base, emitter and collector terminals; at least one current drive transistor having emitter, base and collector terminals with the base-emitter path thereof coupled between said input means and the base of said at least one output transistor, said one current drive transistor providing a turn-on drive current for said one output transistor when binary logic signals concurrently applied to said input means reach a predetermined logical level; resistance means being connectible between a voltage supply terminal and respective ones of said input means, said one current drive transistor, and said one output transistor for biasing same and biasing said one output transistor and said one current drive transistor non-conducting in the absence of binary logic signals at a predetermined logic level concurrently applied to said input means; a discharge circuit means including a transistor having its base and collector regions resistively connected to the base of said one output transistor and its emitter being connectible to a reference potential said collector region also being resistively coupled to said reference potential for supplying a current conducting path for leakage current in said at least one output transistor so as to prevent said at least one output transistor from turning on due to said leakage current.

Claim 12

A logic circuit according to claim 6 wherein said discharge circuit includes: a first resistor coupled between the collector of said first transistor and the base of said at least one output transistor; a second resistor coupled between the base of said first transistor and the base of said at least one output transistor; and a third resistor coupled between the collector of said transistor and said reference potential.