Patent US4409680A successfully refreshed from Google Patents.
US4409680A
Expired / Lapsed
US
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High speed write control for synchronous registers
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1981-08-27
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Granted: 1983-10-11
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Expires: 2001-08-27
Abstract
Abstract An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.
Inventors
- 👤 Vernon K. Schnathorst
- 👤 Gary T. Bastian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:32
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/38
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
142 words
An electronic circuit for controlling data in a bank of D-type, master-slave flip-flops synchronized to a multiple phase clock, comprising: a first field effect transistor having its drain electrode connected to receive a first phase signal from said clock, having its source electrode connected to said bank of flip-flops to control the entry of data into said bank of flip-flops, and having a gate electrode; a bootstrapping field effect transistor having its source electrode connected to said gate electrode of said first field effect transistor, having its drain electrode connected to a source of write command signals, and having its gate electrode connected to a source of voltage which is substantially identical to said write command signals in magnitude; and means for connecting said source electrode of said first field effect transistor to ground potential whenever a write command signal is absent.
Claim 2
Dependent Claim
142 words
An electronic circuit for controlling data in a bank of D-type, master-slave flip-flops synchronized to a multiple phase clock, comprising: a first field effect transistor having its drain electrode connected to receive a first phase signal from said clock, having its source electrode connected to said bank of flip-flops to control the entry of data into said bank of flip-flops, and having a gate electrode; a bootstrapping field effect transistor having its source electrode connected to said gate electrode of said first field effect transistor, having its drain electrode connected to a source of write command signals, and having its gate electrode connected to a source of voltage which is substantially identical to said write command signals in magnitude; and means for connecting said source electrode of said first field effect transistor to ground potential whenever a write command signal is absent.
Claim 3
Dependent Claim
18 words
The circuit recited in claim 1, wherein said multiple phase clock generates two phase signals nonoverlapping in time.
Claim 4
Dependent Claim
24 words
The circuit recited in claim 2, wherein the onset of said write command signals precedes in time the onset of said first phase signals.
Claim 5
Dependent Claim
15 words
The circuit recited in claim 3, wherein said field effect transistors are enhancement mode devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |