Method and circuit for synchronization

Claim 1

A method for synchronizing switching mechanisms or program sequences to an external frame clock pulse comprising the steps of: after a given period of time sufficient for the switching mechanism or program sequences to have completed one cycle of operation, enabling the switching mechanism or program to be restarted; and after enabling, immediately generating an internal clock pulse for the restarting of the switching mechanism or program upon (a) the appearance of the leading edge of the external clock pulse within a further given period of time, (b) the detection of the presence of the external clock pulse at the time of enabling indicating that the leading edge of the external clock pulse has appeared earlier in time, or (c) the termination of said further given period of time if the leading edge of the external clock pulse has not been detected by the end of this further given period of time.

Claim 2

A method for synchronizing switching mechanisms or program sequences to an external frame clock pulse comprising the steps of: after a given period of time sufficient for the switching mechanism or program sequences to have completed one cycle of operation, enabling the switching mechanism or program to be restarted; and after enabling, immediately generating an internal clock pulse for the restarting of the switching mechanism or program upon (a) the appearance of the leading edge of the external clock pulse within a further given period of time, (b) the detection of the presence of the external clock pulse at the time of enabling indicating that the leading edge of the external clock pulse has appeared earlier in time, or (c) the termination of said further given period of time if the leading edge of the external clock pulse has not been detected by the end of this further given period of time.

Claim 4

An apparatus for synchronizing a switching mechanism or a program sequence to an external frame clock pulse whose duration is longer than the time required for said switching mechanism or program sequence to complete one cycle of operation comprising: an oscillator having its output connected to the input of a frequency divider chain having an output for providing an internal frame clock pulse for the switching mechanism or program sequence; a first decoder means having its input connected to said divider chain for producing an output pulse whenever said divider chain reaches a first predetermined state corresponding to said time required for the switching mechanism or program sequence to complete one cycle of operation; a second decoder means having its input connected to said divider chain for producing an output pulse whenever said divider chain reaches a second predetermined state after said first predetermined state; a memory having its input connected to the output of said first decoder means and its output connected to the enabling input of an AND circuit to whose other input is applied the external clock pulse; and an OR circuit having a first input connected to the output of said AND circuit, a second input connected to the output of said second decoder means and its output connected to a reset input of said divider chain and to an erase input of said memory; whereby an internal frame clock pulse is produced immediately upon detection of the external clock pulse during the time period between said first and second predetermined states or upon reaching said second predetermined state without the detection of an external frame clock pulse.

Claim 5

An apparatus for synchronizing a switching mechanism or a program sequence to an external frame clock pulse whose duration is longer than the time required for said switching mechanism or program sequence to complete one cycle of operation comprising: an oscillator having its output connected to the input of a frequency divider chain having an output for providing an internal frame clock pulse for the switching mechanism or program sequence; a first decoder means having its input connected to said divider chain for producing an output pulse whenever said divider chain reaches a first predetermined state corresponding to said time required for the switching mechanism or program sequence to complete one cycle of operation; a second decoder means having its input connected to said divider chain for producing an output pulse whenever said divider chain reaches a second predetermined state after said first predetermined state; a memory having its input connected to the output of said first decoder means and its output connected to the enabling input of an AND circuit to whose other input is applied the external clock pulse; and an OR circuit having a first input connected to the output of said AND circuit, a second input connected to the output of said second decoder means and its output connected to a reset input of said divider chain and to an erase input of said memory; whereby an internal frame clock pulse is produced immediately upon detection of the external clock pulse during the time period between said first and second predetermined states or upon reaching said second predetermined state without the detection of an external frame clock pulse.