Circuit arrangement for correcting slip errors in receiver of cyclic binary codes

Claim 1

In a receiver for cyclic binary codes forming n-bit code words with k information bits and (n-k) redundancy bits, the bits of each code word normally constituting the coefficients of a composite polynomial which is a multiple of a predetermined generator polynomial, in combination: a shift register having an input connected to a communication channel carrying an unbroken succession of n-bit code words arriving during consecutive transmission cycles, said shift register including a group of n intermediate stages for the temporary storage of the bits of an incoming code word to be decoded, at least one initial stage upstream of said intermediate stages for the temporary storage of the first bit of an immediately succeeding code word, and at least one terminal stage downstream of said intermediate stages for the temporary storage of the last bit of an immediately preceding code word; a divider with a dividend input connected only to said intermediate stages, a divisor input connected to a source of said generator polynomial, and output means carrying bits of a remainder resulting from the division of said generator polynomial into the composite polynomial defined by said n bits; timing means for enabling the readout to said dividend input, during a predetermined period at the end of every n-bit transmission cycle, of the bits stored in said n intermediate stages; discriminating means connected to said output means for generating a first signal in response to said remainder being zero, a second signal in response to said remainder having values indicative of a backward slip of the stored code word by a number of bit positions not exceeding the number of said initial stages, and a third signal in response to said remainder having values indicative of a forward slip of the stored code word by a number of bit positions not exceeding the number of said terminal stages; gate means connected to said intermediate stages and to said discriminator means for reading out the stored code word to a load in response to said first signal; and stepping means for said shift register connected to said output means for shifting the stored bits forward in response to said second signal and backward in response to said third signal, within said predetermined period, to an extent compensating for the slip indicated by said remainder, thereby enabling the readout of a corrected version of said stored code word to the load.