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US4408189A
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Method and apparatus for code conversion of binary to multilevel signals
Assignee: Nortel Networks Ltd
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Filing: 1981-05-18
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Granted: 1983-10-04
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Expires: 2001-05-18
Abstract
Abstract A method and apparatus for converting a binary signal to one having quaternary-level symbols with no d-c component. To achieve this, the running digital sum is limited by selectively inverting words within each frame of (n) symbols. A separate (n+1)th symbol is added to each frame to indicate the selective inversion of the words, so that the correct polarity of the (n) symbols can be re-established.
Inventors
- 👤 Malcolm C. Betts
- 👤 Alan F. Graves
- 👤 Frederick M. Pascoe
- 👤 James E. Dilley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:52
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4919; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1496
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
163 words
A code converter comprising: means for converting blocks of binary bits into words of multilevel symbols, the words being grouped into frames; a running digital sum counter for determining the running digital sum of all previously converted multilevel symbol words; a digital sum variation counter for determining the digital sum variation of each word; means responsive to the counters for inverting selected words so as to minimize the accumulated running digital sum of the previously converted multilevel symbol words, and the selected words; characterized by: means for including a separate multilevel symbol at the end of each frame to indicate the inversion of said selected words; and means for initializing the digital sum variation counter at the beginning of each word to a value which compensates for the digital sum variation of the separate multilevel symbol, whereby the polarity of the digital sum variation of the current word may be compared against that of the preceding running digital sum to reestablish frme synchronization.
Claim 2
Dependent Claim
163 words
A code converter comprising: means for converting blocks of binary bits into words of multilevel symbols, the words being grouped into frames; a running digital sum counter for determining the running digital sum of all previously converted multilevel symbol words; a digital sum variation counter for determining the digital sum variation of each word; means responsive to the counters for inverting selected words so as to minimize the accumulated running digital sum of the previously converted multilevel symbol words, and the selected words; characterized by: means for including a separate multilevel symbol at the end of each frame to indicate the inversion of said selected words; and means for initializing the digital sum variation counter at the beginning of each word to a value which compensates for the digital sum variation of the separate multilevel symbol, whereby the polarity of the digital sum variation of the current word may be compared against that of the preceding running digital sum to reestablish frme synchronization.
Claim 3
Dependent Claim
84 words
A code converter as defined in claim 1 in which each frame has (n+1) quaternary-level symbols; and in which the converter includes: means for dividing each frame into first and second words each having n/2 quaternary-level symbols, and into the additional (n+1)th quaternary-level symbol; means for converting a block of n binary bits into the n/2 quaternary-level symbols of one word; means for utilizing all four states of the separate (n+1)th quaternary-level symbol to indicate the selective inversion of both words in each frame.
Claim 4
Dependent Claim
102 words
A code converter as defined in claim 1 in which each frame has (n+1) quaternary-level symbols in which m frames form one multiframe of the binary signal; and in which the converter includes: means for dividing the binary signal into blocks of 2n binary bits; means for converting each block to n quaternary-level symbols; and means for altering one of the polarity and magnitude parameters of each separate (n+1)th quaternary-level symbol to indicate the selective substitution of inverted symbols for the word in each frame, and for altering the other parameter to identify every (m)th frame, whereby multiframe synchronization can be restored.
Claim 5
Dependent Claim
133 words
A code converter as defined in claim 2 in which the binary signal is further divided into pairs of binary bits, one bit of each pair determining the magnitude of one of the symbols and the other bit determining the polarity of that symbol; means responsive to each maximum or minimum magnitude bit to cause the stored count to change by 3 or 1 respectively, and responsive to each positive or negative polarity bit to determine the direction of that change; and means for determining the polarity of the stored count at the end of each of the two words in the digital sum variation counter against the polarity of the previously stored count in the running digital sum counter and for generating the polarity and magnitude of the additional multilevel symbol therefrom.
Claim 6
Dependent Claim
176 words
A code converter for decoding a signal having quaternary-level symbols of the type from the converter defined in claim 2, comprising: means for converting the quaternary-level symbols of the two words of each frame to binary signals; and means for establishing frame synchronization for the words characterized by: a digital sum variation counter for storing a count at the end of ech word representative of the relative magnitude and polarity of ech of the symbols, and a running digital sum counter for storing a count representative of the relative magnitude and polarity of each of the symbols prior to that word; means responsive to a like polarity of the count stored in each of the counters to reduce the absolute count in the running digital sum counter and thereby converge the latter count to its correct value; and means responsive to a selected number of like polarities of the counts stored in each of the counters for shifting the phase of the converting means by a sub-multiple of each frame, so as to reestablish from synchronization.
Claim 7
Dependent Claim
94 words
A code converter as defined in claim 4 in which: the relative magnitude of the balanced quarternary-level symbols is +3, +1, -1 and -3; said digital sum variation counter is initialized to a value of -2 at the beginning of the first word and a value of -1 at the beginning of the second word; and the relative magnitude of the additional (n+1)th quaternary-level symbol for the non-inverted and inverted words is: ______________________________________
1st Word 2nd Word Additional Symbol Magnitude
______________________________________
inverted inverted +3
inverted non-inverted
+1
non-inverted
inverted -1
non-inverted
non-inverted
-3
______________________________________
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |