Pcm transmission system

Claim 2

A pulse code modulation transmission system employing alternate polarity transmission of n-bit pulse code modulation words and having reduced disparity and a zero direct current component, where n is an integer greater than one, comprising: an input for said code words; first means coupled to said input to produce a first control signal for each of said code words having a number of binary 1 bits less than n/2; second means coupled to said first means responsive to said first control signal to complement each of said code words producing said first control signal; third means coupled to said first and second means to produce a single polarity violation of said alternate polarity transmission for each of said complemented code words, said third means producing adjacent ones of said single polarity violations with opposite polarity, each of said adjacent ones of said single polarity violations with opposite polarity being associated with a different one of adjacent ones of said complemented code words; fourth means coupled to said third means to detect said polarity violations and produce a second control signal in response to each of said polarity violations; and fifth means coupled to said fourth means responsive to said second control signal to complement said complemented code words to return said complemented code words to their original form as present at said input.

Claim 3

A system according to claim 1, wherein said second means includes a time delay means coupled to said input to delay said code words by a time interval equal to n bit times, and logic circuitry coupled to said time delay means and said first means to complement each of said code words producing said first control signal.

Claim 4

A system according to claim 2, wherein said time delay means includes a first shift register having n stages.

Claim 5

A system according to claim 3, wherein said first means includes a selector coupled to said input to produce said first control signal, a first flip flop, first logic circuitry coupled between said selector and said first flip flop to couple said first control signal to said first flip flop, a second flip flop, second logic circuitry coupled between said first flip flop and said second flip flop to transfer the state of said first flip flop to said second flip flop, and third logic circuitry coupled to said second flip flop and said first shift register to complement said code words during the presence of said first control signal.

Claim 6

A system according to claim 4, wherein said third means includes a third flip flop, fourth logic circuitry coupled between said selector and said third flip flop to transfer the complement of said first control signal to said third flip flop, fifth logic circuitry coupled to said third logic circuitry and said fourth logic circuitry to provide said polarity violaTions for each of said words producing said first control signal and to provide said code words and said complemented code words with said polarity violations for coupling to said fourth means, and sixth logic circuitry coupled to said third flip flop, said fourth logic circuitry and said fifth logic circuitry to store the polarity of a preceding one of said polarity violations to compare the polarity of the first pulse to be transmitted upon occurrence of a new one of said polarity violations with the polarity of said preceding one of said polarity violations, and to provide said new one of said polarity violations with a polarity opposite to the polarity of said preceding one of said polarity violations.

Claim 7

A system according to claim 5, wherein said fourth means includes a polarity detector coupled to said third means to detect said polarity violations and to produce a negative output signal when said polarity violations are negative and a positive output signal when said polarity violations are positive, seventh logic circuitry coupled to said polarity detector responsive to said negative and positive output signals to produce said second control signal, a retiming circuit coupled to said third means to delay said bits of said code words by p bit times, where p is an integer less than n, and a clock circuit including a counter to produce timing signals defining bit times m1, m2 . . . mn.

Claim 8

A system according to claim 6, wherein said retiming circuit includes a second shift register having p stages.

Claim 9

A system according to claim 7, wherein said fifth means includes eighth logic circuitry coupled to said seventh logic circuitry to provide at the output thereof said code words when said second control signal is absent and a complement of said complemented code words when said second control signal is present.

Claim 10

A system according to claim 8, further including a word synchronization circuit including ninth logic circuitry coupled to said seventh logic circuitry and said counter to set said counter to a bit time mB when said second control signal appears in the time interval bounded by bit times m1 and m(B - 1), inclusive, where B is equal to n/2 and p is equal to ((n/2) + 1) when n is an even integer.

Claim 11

A pulse code modulation transmission circuit employing alternate polarity transmission of n-bit pulse code modulation words and having reduced disparity and a zero direct current component, where n is an integer greater than one, comprising: an input for said code words; first means coupled to said input to produce a control signal for each of said code words having a number of binary 1 bits less than n/2; second means coupled to said first means responsive to said control signal to complement each of said code words producing said control signal; and third means coupled to said first and second means to produce a single polarity violation of said alternate polarity transmission for each of said complemented code words, said third means producing adjacent ones of said single polarity violations with opposite polarity, each of said adjacent ones of said single polarity violations with opposite polarity being associated with a different one of adjacent ones of said complemented code words.

Claim 12

A pulse code modulation transmission circuit employing alternate polarity transmission of n-bit pulse code modulation words and having reduced disparity and a zero direct current component, where n is an integer greater than one, comprising: an input for said code words; first means coupled to said input to produce a control signal for each of said code words having a number of binary 1 bits less than n/2; second means coupled to said first means responsive to said control signal to complement each of said code words producing said control signal; and third means coupled to said first and second means to produce a single polarity violation of said alternate polarity transmission for each of said complemented code words, said third means producing adjacent ones of said single polarity violations with opposite polarity, each of said adjacent ones of said single polarity violations with opposite polarity being associated with a different one of adjacent ones of said complemented code words.

Claim 13

A transmission circuit according to claim 10, wherein said second means includes a time delay means coupled to said input to delay said code words by a time interval equal to n bit times, and logic circuitry coupled to said time delay means and said first means to complement each of said code words producing said control signal.

Claim 14

A transmission circuit according to claim 11, wherein said time delay means includes a first shift register having n stages.

Claim 15

A transmission circuit according to claim 12, wherein said first means includes a selector coupled to said input to produce said control signal, a first flip flop, first logic circuitry coupled between said selector and said first flip flop to couple said control signal to said first flip flop, a second flip flop, second logic circuitry coupled between said first flip flop and said second flip flop to transfer the state of said first flip flop to said second flip flop, and third logic circuitry coupled to said second flip flop and said first shift register to complement said code words during the presence of said control signal.

Claim 16

A transmission circuit according to claim 13, wherein said third means includes a third flip flop, fourth logic circuitry coupled between said selector and said third flip flop to transfer the complement of said control signal to said third flip flop, fifth logic circuitry coupled to said third logic circuitry and said fourth logic circuitry to provide said polarity violations for each of said words producing said control signal and to provide said code words and said complemented code words with said polarity violations for coupling to said fourth means, and sixth logic circuitry coupled to said third flip flop, said fourth logic circuitry and said fifth logic circuitry to store the polarity of a preceding one of said polarity violations, to compare the polarity of the first pulse to be transmitted upon occurence of a new one of said polarity violations with the polarity of said preceding one of said polarity violations, and to provide said new one of said polarity violations with a polarity opposite to the polarity of said preceding one of said polarity violations.

Claim 17

A pulse code modulation receiving circuit receiving alternate polarity n-bit pulse code modulation words including said code words in direct and complemented form with each of the adjacent ones of said code words in complemented form being signalled by a different one of adjacent opposite polarity single polarity violations of said alternate polarity code words, where n is equal to an integer greater than one, comprising: an input for said code words; first means coupled to said input to detect said polarity violations and produce a control signal in response to each of said polarity violations; and second means coupled to said first means responsive to said control signal to complement said code words in complemented form to return said code words in complemented form to their original form prior to complementing in a transmission circuit.

Claim 18

A pulse code modulation receiving circuit receiving alternate polarity n-bit pulse code modulation words including said code words in direct and complemented form with each of the adjacent ones of said code words in complemented form being signalled by a different one of adjacent opposite polarity single polarity violations of said alternate polarity code words, where n is equal to an integer greater than one, comprising: an input for said code words; first means coupled to said input to detect said polarity violations and produce a control signal in response to each of said polarity violations; and second means coupled to said first means responsive to said control signal to complement said code words in complemented form to return said code words in complemented form to their original form prior to complementing in a transmission circuit.

Claim 19

A receiving circuit according to claim 15, wherein said first means includes a polarity detector coupled to said input to detect said polarity violations and to produce a negative output signal when said polarity violations are negative and a positive output signal when said polarity violations are positive, first logic circuitry coupled to said polarity detector responsive to said negative and positive output signals to produce said control signal, a retiming circuit coupled to said input to delay said bits of said code words by p bit times, where p is an integer less than n, and a clock circuit including a counter to produce timing signals defining bit times m1, m2 . . . mn.

Claim 20

A receiving circuit according to claim 16, wherein said retiming circuit includes a second shift register having p stages.

Claim 21

A receiving circuit according to claim 17, wherein said second means includes second logic circuitry coupled to said first logic circuitry to provide at the output thereof said code words in direct form when said control signal is absent and a complement of said code words in complemented form when said control signal is present.

Claim 22

A receiving circuit according to claim 18, further including a word synchronization circuit including third logic circuitry coupled to said first logic circuitry and said counter to set said counter to a biT time mB when said control signal appears in the time interval bounded by bit times m1 and m(B - 1), inclusive, where B is equal to n/2 and p is equal to ((n/2) + 1) when n is an even integer.

Claim 23

A word synchronization circuit for a pulse code modulation receiving circuit receiving alternate polarity n-bit pulse code modulation words including said code words in direct and complemented form with each of the adjacent ones of said code words in complemented form being signalled by a selected one of single polarity polarity violations of said alternate polarity code words and a different one of adjacent opposite polarity single polarity violations of said alternate polarity code words, where n is equal to an integer greater than one, comprising: an input for said code words; a polarity detector coupled to said input to detect said polarity violations and to produce a negative output signal when said polarity violations are negative and a positive output signal when said polarity violations are positive; first logic circuitry coupled to said polarity detector responsive to said negative and positive output signals to produce a control signal; a shift register having p stages coupled to said input to delay said bits of said code words by p bit times, where p is an integer less than n; a clock circuit including a counter to produce timing signals defining bit times m1, m2 . . . mn; and second logic circuitry coupled to said first logic circuitry and said counter to set said counter to a bit time mB when said control signal appears in the time interval bounded by bit times m1 and m(B - 1), inclusive, where B is equal to n/2 and p is equal to ((n/2) + 1) when n is an even integer for signalling by said opposite polarity single polarity violations and where B is equal to ((n/2) + 1) and p is equal to n/2 when n is an even integer for signalling by said single polarity polarity violations.

Claim 24

A word synchronization circuit for a pulse code modulation receiving circuit receiving alternate polarity n-bit pulse code modulation words including said code words in direct and complemented form with each of the adjacent ones of said code words in complemented form being signalled by a selected one of single polarity polarity violations of said alternate polarity code words and a different one of adjacent opposite polarity single polarity violations of said alternate polarity code words, where n is equal to an integer greater than one, comprising: an input for said code words; a polarity detector coupled to said input to detect said polarity violations and to produce a negative output signal when said polarity violations are negative and a positive output signal when said polarity violations are positive; first logic circuitry coupled to said polarity detector responsive to said negative and positive output signals to produce a control signal; a shift register having p stages coupled to said input to delay said bits of said code words by p bit times, where p is an integer less than n; a clock circuit including a counter to produce timing signals defining bit times m1, m2 . . . mn; and second logic circuitry coupled to said first logic circuitry and said counter to set said counter to a bit time mB when said control signal appears in the time interval bounded by bit times m1 and m(B - 1), inclusive, where B is equal to n/2 and p is equal to ((n/2) + 1) when n is an even integer for signalling by said opposite polarity single polarity violations and where B is equal to ((n/2) + 1) and p is equal to n/2 when n is an even integer for signalling by said single polarity polarity violations.