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US3753113A Expired / Lapsed US ⏱️ 0.0 years remaining

Multilevel code signal transmission system

Assignee: NEC Corp
•
Filing: 1971-06-21
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Granted: 1973-08-14
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Expires: 1991-06-21
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Abstract

Abstract A binary code is converted into a multilevel code having an average value of zero over a period of time. A group of n multilevel digits is generated representing the same information conveyed by m X n binary bits. Each digit is a (2m+ k)-level digit. One of said n digits represents the information content of m-1 binary bits as well as polarity inversion and synchronization information. The remaining n-1 multilevel digits represent the information content of the remaining m(n-1)+1 binary bits. The integral of the transmitted n-digit codes is converged to zero level. The transmitted n-digit codes are integrated by continually adding the sum of the levels of the transmitted code to the stored sum to generate a new sum or integral. The sign of the integral is compared with the sign of the sum of levels of the currently generated n-digit code. If the signs are the same, each digit of the n-digit code is polarity inverted. The first of the n digits uses only levels of one polarity when the m-1 binary bits are converted into a single multilevel digit. Consequently, whether or not any given n-digit code has been polarity inverted can be detected by detecting the polarity of the first digit. Thus, the first digit carries the total information of m bits by using one of 2m levels excluding k preselected levels. The remaining (n-1) digits are not inhibited to use those preselected levels. However, the first digit is not at those preselected levels. This feature is used at a receiver to obtain word or block synchronization. At the receiver, a sync pulse is generated for every n digit received. If the receiver is synchronized properly, the sync pulse will be in time coincidence with the first digit of each n-digit code. The presence of one of those preselected levels in coincidence with any sync pulse indicates an out of phase condition and the sync pulse is shifted by one digit time.

Inventors

  • 👤 R Maruta
  • 👤 K Kawai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 02:57
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4919

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 510 words
A digital information communication system comprising: a transmitting apparatus for converting each block of (nxm) binary bits in a binary signal into corresponding blocks of n multilevel digits, each of said multilevel digits being (2m+k)level digit, where n, m and k are positive integers, and for transmitting said blocks of n multilevel digits, said apparatus comprising, a. first means for converting m(n-1)+1 of said binary bits in a block into n-1 level-indicating signals consisting of one or more binary characters, where each one of said level-indicating signals indicates one of (2m+k) levels being symmetrical about zero, b. second means for converting the remaining m-1 binary bits of said block of (nxm) binary bits into a single level-indicating signal, said second means being adapted to convert said m-1 bits into non-zero level indicating signals of a first polarity, c. polarity inversion means responsive to a polarity inversion control signal for converting each level-indicating signal from said first and second means into an output level-indicating signal, respectively, wherein corresponding input and output level-indicating signals indicate equal amplitude opposite polarity levels, and responsive to the absence of said polarity inversion control signal for passing said level-indicating signals from said first and second means to the output thereof without polarity inversion, d. means for converting n simultaneously occurring polaritycontrolled level-indicating signals from said polarity inversion means into n serial (2m+k)-level digits, said latter digits having respective amplitudes and polarities corresponding to said polarity-controlled level-indicating signals; and e. convolution means for generating said polarity inversion control signal in response to the algebraic sum of the levels indicated by the most recent block of said n level-indicating signals from said first and second means being of the same polarity as the algebraic sum of the prior said multilevel digits, a receiving apparatus for receiving said blocks of n multilevel digits and for reconverting them back into blocks of (n X m) binary bits, including, f. means responsive to each received multilevel digit for generating a level-representing signal representing the amplitude and polarity of said digit, g. means responsive to said received multilevel digits for generating timing pulses, synchronized with said received multilevel digits, h. means responsive to said level-representing signals and said timing pulses for generating a block synchronizing pulse in timed relationship with a specific digit in each of said received blocks, i. logic means responsive to said block sync pulses and said level-representing signals for generating a polarity inversion control signal when said specific digit of a code has a polarity opposite to said first polarity, j. polarity inversion means responsive to said polarity inversion control signal generated by said logic means for converting n successive level-representing signals into polarity-controlled n level-representing signals which indicate like amplitude but opposite polarity, and responsive to the absence of said polarity inversion control signal for passing n successive level-representing signals from said generating means directly, without polarity indication change, to the output thereof, and k. multilevel-to-binary converters means for converting the outputs from said polarity inversion means into a corresponding group of (m X n) binary bits.
Claim 2
Dependent Claim 510 words
A digital information communication system comprising: a transmitting apparatus for converting each block of (nxm) binary bits in a binary signal into corresponding blocks of n multilevel digits, each of said multilevel digits being (2m+k)level digit, where n, m and k are positive integers, and for transmitting said blocks of n multilevel digits, said apparatus comprising, a. first means for converting m(n-1)+1 of said binary bits in a block into n-1 level-indicating signals consisting of one or more binary characters, where each one of said level-indicating signals indicates one of (2m+k) levels being symmetrical about zero, b. second means for converting the remaining m-1 binary bits of said block of (nxm) binary bits into a single level-indicating signal, said second means being adapted to convert said m-1 bits into non-zero level indicating signals of a first polarity, c. polarity inversion means responsive to a polarity inversion control signal for converting each level-indicating signal from said first and second means into an output level-indicating signal, respectively, wherein corresponding input and output level-indicating signals indicate equal amplitude opposite polarity levels, and responsive to the absence of said polarity inversion control signal for passing said level-indicating signals from said first and second means to the output thereof without polarity inversion, d. means for converting n simultaneously occurring polaritycontrolled level-indicating signals from said polarity inversion means into n serial (2m+k)-level digits, said latter digits having respective amplitudes and polarities corresponding to said polarity-controlled level-indicating signals; and e. convolution means for generating said polarity inversion control signal in response to the algebraic sum of the levels indicated by the most recent block of said n level-indicating signals from said first and second means being of the same polarity as the algebraic sum of the prior said multilevel digits, a receiving apparatus for receiving said blocks of n multilevel digits and for reconverting them back into blocks of (n X m) binary bits, including, f. means responsive to each received multilevel digit for generating a level-representing signal representing the amplitude and polarity of said digit, g. means responsive to said received multilevel digits for generating timing pulses, synchronized with said received multilevel digits, h. means responsive to said level-representing signals and said timing pulses for generating a block synchronizing pulse in timed relationship with a specific digit in each of said received blocks, i. logic means responsive to said block sync pulses and said level-representing signals for generating a polarity inversion control signal when said specific digit of a code has a polarity opposite to said first polarity, j. polarity inversion means responsive to said polarity inversion control signal generated by said logic means for converting n successive level-representing signals into polarity-controlled n level-representing signals which indicate like amplitude but opposite polarity, and responsive to the absence of said polarity inversion control signal for passing n successive level-representing signals from said generating means directly, without polarity indication change, to the output thereof, and k. multilevel-to-binary converters means for converting the outputs from said polarity inversion means into a corresponding group of (m X n) binary bits.
Claim 3
Dependent Claim 209 words
The system as claimed in claim 1 wherein said convolution means comprises, a. means responsive to each group of n level-indicating signals from said first and second means for generating a first algebraic sum indication code (W5 - W1) indicating the levels represented by said n level-indicating signals and for generating a second algebraic sum indication code which corresponds to a polarity inversion of said first algebraic sum, b. storage means for storing an integral sum indication code indicating the integral sum of the levels represented by said n level-indicating signals, c. comparing means For comparing the polarity of said stored integral sum indication code with the polarity of said first algebraic sum indication code, d. generating means responsive to said comparing means for generating said polarity inversion control signal when the polarities of said integral sum indication code and said first algebraic sum indication code are the same, and e. selecting means responsive to said comparing means for adding said first algebraic sum indication code to said stored integral sum indication code when said polarities are opposite and for adding said second algebraic sum indication code to said stored integral sum indication code when said polarities are the same, to form an updated stored integral sum indication code.
Claim 4
Dependent Claim 149 words
The system as claimed in claim 1 wherein said block synchronizing means in said receiver comprises, a. synchronous circuit means responsive to the coincidence of pulses applied to first and second input terminals thereof for generating a shift pulse, b. logic means, connected to the output of said level-indicating signal generating means, for developing a first pulse each time the level-indicating signal from said generating means indicates one or more specific levels, said first pulse being applied to the first input of said synchronous circuit means, c. divider means responsive to input pulses applied thereto for generating one output pulse for every n input pulse thereto, said output pulses being applied to the second input terminal of said synchronous circuit means, d. shift means responsive to said timing pulses and said shift pulses for applying every timing pulse, not in coincidence with a shift pulse, to said divider means.
Claim 5
Dependent Claim 123 words
The system as claimed in claim 3 wherein logic means for generating a polarity inversion control signal comprises, a. bistable circuit means providing said polarity inversion control signal as an output in one stable state and a not polarity inversion control signal in the other stable state, b. gating means connected to the output of said level-indicating signal generating means for generating a gating pulse when said received digit has a second polarity, opposite to said first polarity, and c. means for triggering said bistable circuit in response to each pulse from said divider means, said bistable circuit being triggered to the first state when said gating pulse is present and being triggered to the second state when said gating pulse is absent.
Claim 6
Dependent Claim 382 words
A system as claimed in claim 4 wherein said first means comprises, a. means for converting each group of m of said binary bits into a first level-indicating signal (qi,l) when the remaining one binary bit (br) has a first value (e.g. 1), the conversion being a one-to-one relation between the 2m possible bit patterns of said group of m bits and 2m levels of said 2m+k levels, the latter being indicated by said first level-indicating signals and excluding a first group of k specific levels (li) in said 2m+k levels, thereby to generate a first sub-set (A1) of the level indicating signals, b. means for converting each group of m of said binary bits into an intermediate level-indicating signal when said remaining one binary bit (br) has a second value (e.g. 0), the conversion being a one-to-one relation between the 2m possible bit patterns of said group of m bits and 2m levels of said 2m+k levels, the latter being indicated by said intermediate level-indicating signals and excluding said first group of k specific levels, thereby to generate an intermediate sub-set (A1'') of level-indicating signals, c. means for converting at least one level-indicating signal in said intermediate sub-set (A1''), which indicates one of a second group of k specific levels (lj'') excluding said first group of k specific levels (li), into a level-indicating signal indicating one of said first group of k specific levels (li), thereby to generate a second sub-set (A22) of the level-indicating signals, which includes at least one level-indicating signal indicating one of said first group of k specific levels (li) and excludes the level-indicating signals indicating said second group of k specific levels (lj''), d. means for converting each of the remaining level-indicating signals in said intermediate sub-set (A1''), which indicates one of the remaining levels excluding said first and second groups of k specific levels (li, lj''), into a level-indicating signal indicating one of said first group of k specific levels and one of said second group of k specific levels simultaneously, by a one-to-one relation, thereby to generate a third sub-set (A21) of the level-indicating signals, which includes the level-indicating signals each indicating one of said first group of k specific levels (li) and one of said second group of k specific levels (lj'') simultaneously.

References Cited (Backward Citations)

US2700696A Cited
US3369229A Cited
US3521274A Cited
US3569955A Cited
US3611141A Cited
US3587088A Cited
US3623078A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-08-13 1977-02-12 1977-08-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-08-13 1981-02-12 1981-08-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-08-13 1985-02-12 1985-08-14 $7700.00 Window Closed / Lapsed

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