Data processing system having apparatus in a communications subsystem for establishing byte synchronization

Claim 1

In combination with a communication line coupled to a communications subsystem, a data processing system comprising a system bus, at least one central processing unit (CPU), one main memory system, one peripheral controller and said communications subsystem, all coupled in common to the system bus, said communications subsystem including a communications controller coupled to said system bus, a plurality of flexible line adapters (FLAPs), each coupled to said communications controller, and further including typical communication devices such as a modem, a dialing unit, a touch-tone receiver, a cathode ray tube (CRT), a plurality of each of said typical devices coupled to one each of said FLAPs, an apparatus in said each of said FLAPs for establishing byte synchronization comprising: (a) a U-bus and an M-bus coupled to each other, and further coupled to said system bus; (b) a microprocessor (μP) coupled to said U-bus; (c) a random access memory (RAM) coupled to said M-bus; (d) a programmable read only memory (PROM) also coupled to said M-bus; (e) a universal synchronous receiver (USRT) coupled to said U-bus for transmitting bytes of information read from said main memory to a selected one of said typical devices via said FLAPs, and receiving bytes of information from said selected one of said typical devices via said FLAPs for writing in said main memory, said bytes of information being transferred in a byte control protocol mode when one of said typical devices generates a sequence of byte timing pulses of which successive pulses are separated by one byte width; and (f) synchronizing means included in said FLAPs and coupled to said USRT and to said typical devices, said synchronizing means synchronizing said bytes of information to the sequence of byte timing pulses.