US3680051A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for maintaining character synchronization in a data communication system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1970-07-29
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Granted: 1972-07-25
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Expires: 1990-07-29
Abstract
Abstract Apparatus for maintaining character synchronization in a data communication system comprises a buffer to store characters being transferred from a communications controller to a terminal device, a shift register connected between the buffer and the terminal device and a source of fill characters which provides characters to fill any gap between message characters provided by the communications controller.
Inventors
- 👤 Ronald W Blessin
- 👤 James A Kennedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:18
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
263 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a character is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; and means for sensing when a message character is loaded into said buffer, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a message character is loaded into said buffer, said means for sensing developing a second signal when a message character is not loaded into said buffer, said means for sensing being coupled to said second gating means, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register.
Claim 2
Dependent Claim
263 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a character is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; and means for sensing when a message character is loaded into said buffer, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a message character is loaded into said buffer, said means for sensing developing a second signal when a message character is not loaded into said buffer, said means for sensing being coupled to said second gating means, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register.
Claim 3
Dependent Claim
265 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a characTer is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; and means for sensing when a message character is loaded into said buffer, said means for sensing being coupled to said second gating means, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a message character is loaded into said buffer, said means for sensing developing a second signal a predetermined time after a message character is loaded into said buffer, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register.
Claim 4
Dependent Claim
265 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a characTer is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; and means for sensing when a message character is loaded into said buffer, said means for sensing being coupled to said second gating means, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a message character is loaded into said buffer, said means for sensing developing a second signal a predetermined time after a message character is loaded into said buffer, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register.
Claim 5
Dependent Claim
44 words
The combination as defined in claim 2 including: means to inhibit said means for sensing from developing said second signal when another message character is loaded into said buffer, said means to inhibit being coupled to said buffer and to said means for sensing.
Claim 6
Dependent Claim
304 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a character is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; means for sensing when a message character is loaded into said buffer, said means for sensing being coupled to said second gating means, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a first message character is loaded into said buffer, said means for sensing developing a second signal a predetermined time after said first message character is loaded into said buffer, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register; and means to inhibit the developing of said second signal when a second message character is loaded into said buffer before the end of said predetermined time, said means to inhibit being coupled to said means for sensing.
Claim 7
Dependent Claim
304 words
In a data communication system having a processor, a memory, a communications controller, a terminal device and a subchannel, said subchannel having the combination comprising: a buffer for storing a message character, said buffer being coupled to said controller; a shift register, said register being coupled to said device; first and second gating means, said first gating means being connected between said buffer and said register; a source of fill characters, said second gating means being connected between said source and said register; means for detecting when each bit of a character is shifted from said register to said device, said means for detecting being coupled to said register, said means for detecting producing a signal pulse when the final bit of a character is shifted from said register; means for sensing when a message character is loaded into said buffer, said means for sensing being coupled to said second gating means, said means for sensing being connected between said buffer and said first gating means, said means for detecting being coupled to said first and to said second gating means, said means for sensing developing a first signal when a first message character is loaded into said buffer, said means for sensing developing a second signal a predetermined time after said first message character is loaded into said buffer, said first signal and said signal pulse causing said first gating means to transfer a message character from said buffer into said register, said second signal and said signal pulse causing said second gating means to transfer a fill character from said source into said register; and means to inhibit the developing of said second signal when a second message character is loaded into said buffer before the end of said predetermined time, said means to inhibit being coupled to said means for sensing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |