Abstract A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base. The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.
In a memory cell having a pair of bipolar transistors cross-coupled by their bases and collectors and an individual load resistor connected to the collectors of each transistor, the improvement comprising: support means; first and second metallic collector contact on said support means; first mesa bipolar transistor on said first collector contact and second mesa bipolar transistor on said second collector contact, said first and second mesa bipolar transistors being separated by a valley and each having a collector, base and emitter; a first resistor in said valley, connected at one end thereof to the collector of said first transistor and the base of said second transistor through apertures in an insulating material; a second resistor in said valley, connected at one end thereof to the collector of said second transistor and the base of said first transistor through apertures on an insulating material; said first and second resistors being connected at their other ends through an aperture in an insulating material there between.
Claim 2
Dependent Claim
164 words
In a memory cell having a pair of bipolar transistors cross-coupled by their bases and collectors and an individual load resistor connected to the collectors of each transistor, the improvement comprising: support means; first and second metallic collector contact on said support means; first mesa bipolar transistor on said first collector contact and second mesa bipolar transistor on said second collector contact, said first and second mesa bipolar transistors being separated by a valley and each having a collector, base and emitter; a first resistor in said valley, connected at one end thereof to the collector of said first transistor and the base of said second transistor through apertures in an insulating material; a second resistor in said valley, connected at one end thereof to the collector of said second transistor and the base of said first transistor through apertures on an insulating material; said first and second resistors being connected at their other ends through an aperture in an insulating material there between.
Claim 3
Dependent Claim
30 words
The memory cell according to claim 1 wherein said first and second resistors are doped polycrystalline resistors and are connected to said first and second transistors by doped polycrystalline conductors.