Method for fabrication of a non-volatile JRAM cell

Claim 1

A method for fabrication of a non-volatile, random-access data storage cell, comprising the steps of: (a) forming channels of one conductivity type separated by areas of the opposite conductivity type on a semiconductor substrate; (b) constructing vertical JFET devices having source regions of said one conductivity type at spaced intervals along said channels; (c) forming multi-dielectric stacks in such a proximity to the source region of each said JFET device so as to capacitively couple said multi-dielectric stacks to said source regions; and (d) forming metal lines for interconnection of said cells and peripheral devices contained on said substrate.

Claim 2

A method for fabrication of a non-volatile, random-access data storage cell, comprising the steps of: (a) forming channels of one conductivity type separated by areas of the opposite conductivity type on a semiconductor substrate; (b) constructing vertical JFET devices having source regions of said one conductivity type at spaced intervals along said channels; (c) forming multi-dielectric stacks in such a proximity to the source region of each said JFET device so as to capacitively couple said multi-dielectric stacks to said source regions; and (d) forming metal lines for interconnection of said cells and peripheral devices contained on said substrate.

Claim 8

A method for fabrication of a non-volatile data storage cell comprising the steps of: (a) patterning a semiconductor substrate by masking and insulating, and subsequently ion-implanting a first dopant material in exposed areas of said substrate to form channel stops; (b) preparing said patterned substrate for further ion-implant by further masking and insulating, and ion-implanting of exposed areas with said first dopant to form sources; (c) forming an insulating layer in desired areas, and subsequently ion-implanting the exposed areas with a second dopant to form word line areas of conductivity opposite that of said substrate; (d) removing selected insulating materials; (e) forming a multi-dielectric stack directly upon selected exposed areas of substrate; (f) removing insulating layer in selected areas to expose substrate; and (g) forming patterns of conductive material for interconnection of said substrate and other elements of cell and other devices on said substrate.

Claim 9

A method for fabrication of a non-volatile data storage cell comprising the steps of: (a) patterning a semiconductor substrate by masking and insulating, and subsequently ion-implanting a first dopant material in exposed areas of said substrate to form channel stops; (b) preparing said patterned substrate for further ion-implant by further masking and insulating, and ion-implanting of exposed areas with said first dopant to form sources; (c) forming an insulating layer in desired areas, and subsequently ion-implanting the exposed areas with a second dopant to form word line areas of conductivity opposite that of said substrate; (d) removing selected insulating materials; (e) forming a multi-dielectric stack directly upon selected exposed areas of substrate; (f) removing insulating layer in selected areas to expose substrate; and (g) forming patterns of conductive material for interconnection of said substrate and other elements of cell and other devices on said substrate.

Claim 10

A method for fabricating a non-volatile data storage cell, comprising the steps of: (a) forming first and second insulating layers on a semiconductor substrate; (b) masking and etching said first and second insulating layers to expose said semiconductor substrate in desired areas; (c) ion-implanting a first dopant material in said exposed areas of semiconductor substrate in a heavy concentration; (d) forming a first thick insulating layer over said ion-implanted areas of semiconductor surface; (e) removing the remainder of said first and second insulating layers and forming in their place a third thin insulating layer; (f) masking said areas covered by a thick insulating layer, and ion-implanting said areas covered by thin insulating layer with said first dopant material in a light concentration; (g) forming a plurality of multi-layer areas, each said area consisting of: (1) a thick layer of semiconductor material, deposited on said semiconductor substrate and having a second dopant material therein to cause it to be of high conductivity for the purpose of providing a gate region for MOSFET devices constructed on the periphery of said semiconductor substrate; (2) a thin insulating layer overlying said thick layer of semiconductor material. (3) a thick insulating layer, overlying said thin insulating layer; (h) doping areas not covered by said multi-layer areas with a second dopant material in a dosage amount sufficient to create areas of conductivity opposite that of said semiconductor substrate; (i) forming a second thick insulator layer over the device except for said multi-layer areas, and areas covered by said first thick insulator layer; (j) masking device areas except for selected said multi-layer areas, removing selected said multi-layer areas to expose said semiconductor substrate; and (k) forming a multi-dielectric stack comprising: (1) a first thin insulating layer overlying said semiconductor substrate; (2) a second thin insulating layer directly upon said first insulating layer; (3) a third insulating layer directly over said second insulating layer; (4) a fourth insulating layer directly over said third insulating layer; (l) etching vias in thick oxide to expose selected substrate locations; and (m) making and forming a layer of conductive material for interconnections.

Claim 11

A method for fabricating a non-volatile data storage cell, comprising the steps of: (a) forming first and second insulating layers on a semiconductor substrate; (b) masking and etching said first and second insulating layers to expose said semiconductor substrate in desired areas; (c) ion-implanting a first dopant material in said exposed areas of semiconductor substrate in a heavy concentration; (d) forming a first thick insulating layer over said ion-implanted areas of semiconductor surface; (e) removing the remainder of said first and second insulating layers and forming in their place a third thin insulating layer; (f) masking said areas covered by a thick insulating layer, and ion-implanting said areas covered by thin insulating layer with said first dopant material in a light concentration; (g) forming a plurality of multi-layer areas, each said area consisting of: (1) a thick layer of semiconductor material, deposited on said semiconductor substrate and having a second dopant material therein to cause it to be of high conductivity for the purpose of providing a gate region for MOSFET devices constructed on the periphery of said semiconductor substrate; (2) a thin insulating layer overlying said thick layer of semiconductor material. (3) a thick insulating layer, overlying said thin insulating layer; (h) doping areas not covered by said multi-layer areas with a second dopant material in a dosage amount sufficient to create areas of conductivity opposite that of said semiconductor substrate; (i) forming a second thick insulator layer over the device except for said multi-layer areas, and areas covered by said first thick insulator layer; (j) masking device areas except for selected said multi-layer areas, removing selected said multi-layer areas to expose said semiconductor substrate; and (k) forming a multi-dielectric stack comprising: (1) a first thin insulating layer overlying said semiconductor substrate; (2) a second thin insulating layer directly upon said first insulating layer; (3) a third insulating layer directly over said second insulating layer; (4) a fourth insulating layer directly over said third insulating layer; (l) etching vias in thick oxide to expose selected substrate locations; and (m) making and forming a layer of conductive material for interconnections.