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US4400866A Expired / Lapsed US ⏱️ 0.0 years remaining

Application of grown oxide bumper insulators to a high-speed VLSI SASMESFET

Assignee: Xerox Corp
•
Filing: 1982-04-05
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Granted: 1983-08-30
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Expires: 2002-04-05
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Abstract

Abstract A semiconductor structure and particularly a high-speed VLSI self-aligned Schottky Metal Semi-Conductor Field Effect Transistor having a relatively high operating frequency and low series resistance, predicated upon very controllable small structure geometries made by the growth of oxide bumper insulators on either side of the schottky barrier. The oxide bumpers width is relatively thicker than the depth of the initial silicon dioxide layer on the substrate surface thereby providing effective separation of the gate from the source and drain respectively. Accordingly, spatial separations between the self-aligned gate-and-drain and gate-and-source can be relatively very closely controlled by varying the doping level of an intermediate polysilicon layer thereby providing controllable differential polysilicon oxidation rates for the bumpers. Thus, the series resistance can be controlled to be relatively low thereby providing a VLSI SASMESFET device that can be operated at relatively high speeds.

Inventors

  • 👤 Keming W. Yeh
  • 👤 Izya Bol

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 11:45
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/80; H10D30/87; H10D62/161; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 168 words
A controllable method of making a VLSI SASMESFET structure having a substrate with an implanted channel, an initial oxide layer disposed on the implanted channel of the substrate, a layer of polysilicon doped with phosphorus disposed on the initial substrate oxide layer coincident with an area defined for a Schottky gate, a silicon nitride layer disposed on the polysilicon layer, and source and drain areas implanted in the substrate on either side of the area defined for the Schottky gate, comprising the steps of: a. oxidizing the polysilicon layer at a rate determined by the doping level and thickness at a predetermined temperature thereof to form oxide insulating bumpers at the ends of the polysilicon layer where the width of the oxide bumpers so formed determined the minimal source-to-gate and drain-to-gate separations for reduced series resistance therebetween; and b. etching away of the silicon nitride layer, the polysilicon layer and the initial silicon dioxide layer to expose the implanted channel in the area that defines the Schottky gate.
Claim 2
Dependent Claim 168 words
A controllable method of making a VLSI SASMESFET structure having a substrate with an implanted channel, an initial oxide layer disposed on the implanted channel of the substrate, a layer of polysilicon doped with phosphorus disposed on the initial substrate oxide layer coincident with an area defined for a Schottky gate, a silicon nitride layer disposed on the polysilicon layer, and source and drain areas implanted in the substrate on either side of the area defined for the Schottky gate, comprising the steps of: a. oxidizing the polysilicon layer at a rate determined by the doping level and thickness at a predetermined temperature thereof to form oxide insulating bumpers at the ends of the polysilicon layer where the width of the oxide bumpers so formed determined the minimal source-to-gate and drain-to-gate separations for reduced series resistance therebetween; and b. etching away of the silicon nitride layer, the polysilicon layer and the initial silicon dioxide layer to expose the implanted channel in the area that defines the Schottky gate.
Claim 3
Dependent Claim 39 words
The controllable method of making a VLSI SASMESFET structure according to claim 1 further including the step of photopatterning and etching windows in the initial silicon dioxide layer to expose the source and drain areas implanted in the substrate.
Claim 4
Dependent Claim 56 words
The controllable method of making a VLSI SASMESFET structure according to claim 2 further including the step of depositing a proper metal on the exposed source and drain areas opened up by the etching of the windows in the initial silicon dioxide layer, and also disposed over and on the area defined for the Schottky gate.
Claim 5
Dependent Claim 19 words
The controllable method of making a VLSI SASMESFET structure according to claim 2 wherein the proper metal is platinum.
Claim 6
Dependent Claim 43 words
The controllable method of making a VLSI SASMESFET structure according to claim 3 further including the step of forming through thermal application to proper metal and the substrate an alloy in operative contact with the substrate where the proper metal has been deposited.
Claim 7
Dependent Claim 24 words
The controllable method of making a VLSI SASMESFET structure according to claim 5 further including the step of etching away all unalloyed proper metal.
Claim 8
Dependent Claim 31 words
The controllable method of making a VLSI SASMESFET structure according to claim 6 wherein the proper metal and the substrate alloy formed in the Schottky gate area is a Schottky barrier.
Claim 9
Dependent Claim 41 words
The controllable method of making a VLSI SASMESFET structure according to claim 5 wherein the proper metal and substrate alloy in operative contact with the exposed source and drain areas opened up by the etching of the windows are ohmic contacts.
Claim 10
Dependent Claim 31 words
The controllable method of making a VLSI SASMESFET structure according to claim 5 further including the step of depositing alternating layers of proper metals over the proper metal and substrate alloy.
Claim 11
Dependent Claim 36 words
The controllable method of making a VLSI SASMESFET structure according to claim 9 wherein the alternating proper metal proximate to and disposed on the proper metal and substrate alloy is an alloy of titanium and tungsten.
Claim 12
Dependent Claim 28 words
The controllable method of making a VLSI SASMESFET structure according to claim 10 wherein the alternating proper metal disposed on the alloy of titanium and tungsten is aluminum.

References Cited (Backward Citations)

US3668481A Cited
US3590471A Cited
US3943622A Cited
US4090289A Cited
US4102733A Cited
US4282647A Cited
DE2824026A1 Cited
US4263605A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-08-29 1987-02-28 1987-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-08-29 1991-02-28 1991-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-08-29 1995-02-28 1995-08-30 $7700.00 Window Closed / Lapsed

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