Patent US4397887A successfully refreshed from Google Patents.
US4397887A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Postponed ROM programming
Assignee: National Semiconductor Corp
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Filing: 1982-08-18
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Granted: 1983-08-09
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Expires: 2002-08-18
Abstract
Abstract A process to program ROM's after the insulation, gates, and interconnect circuitry have been formed by using a contact mask to define openings at the depletion cells, which openings extend beside the gates to the sources and drain so as to allow phosphorus dopant to be diffused sideways under the gates to short out the cell.
Inventors
- 👤 Haluk M. Aytac
- 👤 John F. MacDonald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:59
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
122 words
In the fabrication of a silicon semiconductor field effect memory device wherein spaced apart source and drain areas are formed on a substrate with a channel extending therebetween and a control gate is formed above the channel with an oxide insulating layer covering the gate and device, an improvement to the process that allows the device to be converted into a normally conducting device late in the fabrication process comprising: masking and etching the device so as to create openings to the source and drain areas on the substrate beside the control gate; and doping said source and drain areas through said openings so as to expand said areas toward each other, under said gate, until they form a continuous conduction path.
Claim 2
Dependent Claim
122 words
In the fabrication of a silicon semiconductor field effect memory device wherein spaced apart source and drain areas are formed on a substrate with a channel extending therebetween and a control gate is formed above the channel with an oxide insulating layer covering the gate and device, an improvement to the process that allows the device to be converted into a normally conducting device late in the fabrication process comprising: masking and etching the device so as to create openings to the source and drain areas on the substrate beside the control gate; and doping said source and drain areas through said openings so as to expand said areas toward each other, under said gate, until they form a continuous conduction path.
Claim 3
Dependent Claim
29 words
The process of claim 1 in which said source and drain areas are additionally doped by forming a doped oxide insulating layer on said device and in said opening.
Claim 4
Dependent Claim
19 words
The process of claim 2 in which said doped oxide comprises silicon oxide with about 8 percent phosphorus therein.
Claim 5
Dependent Claim
35 words
The process of claim 1 in which the source and drain areas are additionally doped with phosphorus through said openings and thereafter an insulating oxide layer is formed on said device and in said openings.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-08 | 1987-02-07 | 1987-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-08 | 1991-02-07 | 1991-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-08 | 1995-02-07 | 1995-08-09 | $7700.00 | Window Closed / Lapsed |