Patent US4392298A successfully refreshed from Google Patents.
US4392298A
Expired / Lapsed
US
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Integrated circuit device connection process
Assignee: AT&T Inc
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Filing: 1981-07-27
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Granted: 1983-07-12
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Expires: 2001-07-27
Abstract
Abstract A method for forming electrical interconnections in an integrated circuit which involves forming an insulating layer on the silicon chip on the lower of two conductive layers to be interconnected, opening a window in the insulating layer, filling the window with a metallic plug by a lift-off technique, and then forming an interconnection pattern extending over the layer and contacting the plug.
Inventors
- 👤 Robert A. Barker
- 👤 Edith C. Ong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10P; H10P76/00; H10P76/20; H10P76/202; H10W20/058; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
198 words
The method of forming electrical connections in an integrated circuit device comprising the steps of preparing an integrated circuit device comprising a silicon chip which includes a dielectric coating, providing a two-level photosensitive masking layer over the dielectric coating of which the first level is sensitive to ultraviolet light and the second level is sensitive to visible light, patterning said masking layer in accordance with the pattern of openings desired in the dielectric coating to permit connection therethrough by first irradiating with visible light and patterning the second level and then irradiating with ultraviolet light and patterning the second level, making openings in said coating in accordance with the pattern by reactive ion etching to provide substantially vertical sidewalls in the openings, depositing a conductive layer over the masking layer and in the openings in the dielectric coating of a thickness substantially to match the thickness of the dielectric coating, dissolving the masking layer, thereby lifting off the overlying portion of the conductive layer, while leaving a plug portion of the conductive layer in the opening in the dielectric coating, and forming over the dielectric coating a conductive layer which makes low resistance connection to the plug portion.
Claim 2
Independent Claim
198 words
The method of forming electrical connections in an integrated circuit device comprising the steps of preparing an integrated circuit device comprising a silicon chip which includes a dielectric coating, providing a two-level photosensitive masking layer over the dielectric coating of which the first level is sensitive to ultraviolet light and the second level is sensitive to visible light, patterning said masking layer in accordance with the pattern of openings desired in the dielectric coating to permit connection therethrough by first irradiating with visible light and patterning the second level and then irradiating with ultraviolet light and patterning the second level, making openings in said coating in accordance with the pattern by reactive ion etching to provide substantially vertical sidewalls in the openings, depositing a conductive layer over the masking layer and in the openings in the dielectric coating of a thickness substantially to match the thickness of the dielectric coating, dissolving the masking layer, thereby lifting off the overlying portion of the conductive layer, while leaving a plug portion of the conductive layer in the opening in the dielectric coating, and forming over the dielectric coating a conductive layer which makes low resistance connection to the plug portion.
Claim 3
Dependent Claim
15 words
The method in accordance with claim 1 in which the first-mentioned conductive layer is aluminum.
Claim 4
Dependent Claim
16 words
The method in accordance with claim 2 in which the second-mentioned conductive layer is also aluminum.
Claim 5
Dependent Claim
27 words
The method in accordance with claim 3 in which the dielectric coating is phosphorus-doped silicon oxide and reactive ion etching is used to make the openings therein.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |